EDUCATION

University of Southern California (USC), Los Angeles, California, USA, May 2010

Master of Science, Electrical Engineering. GPA: 3.72/4                

Related coursework: Analog and Non-Linear Integrated Circuit, MOS VLSI Circuit Design, VLSI System Design (A)(B), Mixed-Signal Integrated Circuit Design (A), Digital System Design – Tools and Techniques, Introduction to Digital Image Processing, Modern Solid-State Devices.

National Tsing-Hua University (NTHU), HsinChu, Taiwan, June 2007

Bachelor of Science, Engineering and System Science

Second Major: IC Design Curriculum Program

Related coursework: Analog and Digital circuit design, MEMS manufacture

SKILLS

HDL Proficiency:

VHDL and Verilog for digital logic design, synthesis, and verification of VLSI, ASIC and FPGA based systems

CAD Tools and Engineering Software Applications:

Cadence Composer Schematic Tool, Cadence Virtuoso, Nanosim, NC Verilog, Synopsys Design Analyzer/Compiler, ModelSim, Xilinx ISE/WebPACK, Xilinx Chipscope, Hspice, Matlab

Programming Language:

C++, Visual Basic

PUBLICATION

“IMPROVED HYDROPHOBICITY OF VAPOR COATED CHLOROSILANE SELF ASSEMBLED MONOLAYERS USING EVAPORATIVE DRYING OF SOLVENT AND ANNEALING” By H. S. Khoo, T. W. Huang, Y. F. Chen, M. H. Chen, T.H. Hsu, and F.G. Tseng, Transducers '07, Lyon, France, June 2007

RESEARCH

USC Projects:

Brain Synapses Circuits Design under Sub-threshold Region, 2009                                                                           

·       The target is to lower the power dissipation of synapse circuit

·       The average power saved 74% using TSMC-18 technology

·       Customize brain synapses circuits using Cadence tool-set and test circuits using Hspice

5-Stage Pipelined CPU based on Tomasolu Algorithm using ModelSim with VHDL, 2009

·       Design and verification of MIPS architecture based CPU with branch prediction and speculative execution

·       Implement the design on Digilent Nexys-2 1600K FPGA board

16-Bit Motion Estimator for a DSP by using Cadence and Nanosim, 2008

·       The motion estimator is the core operation performed during video encoding with “16-Bit Absolute Difference Calculator”, “7-Bit Data Pointer”, “4Kb SRAM”

·       Using Cadence to design schematic and layout, and simulate it with Nanosim

Trojan 2D Mesh NoC Router using NC Verilog, 2010

·       Design and synthesis an NoC router network using Verilog code

The “Quarterback” Neural Network using Cadence, 2008

·       The network will simulate a quarterback’s decision map with inputs like excite, pass, etc.

·       Using Cadence to design in schematic and layout

NTHU Projects:

Self-aligned Microdroplet Movement due to Wettability Gradient, 2005 – 2007

·       Building a biomedical chip that could auto-detect diseases (scholarship granted by National Science Council of Taiwan)

·       Manufacture MEMS systems with different hydrophobicity in clean room over 300 hours

·       Design photomasks for biomedical chip manufacturing using Autocad

All-Digital 3-Bit Delay-locked Loop using Cadence and HSPICE, 2006

·       Design DLL using HSPICE, and the layout were verified by DRC, LVS, and post-simulation

CMOS Low-voltage Fully-differential Op-Amp, 2006

·       Design a 3-stage Vdd=1.2v Op-Amp with CMOS 0.25um technology using HSPICE

WORK EXPERIENCE

Second Lieutenant, Military Service, Taiwan, July 2007 – June 2008

·       Taking charge of the warehouse and logistics management

·       Supervising twelve soldiers

LANGUAGE

Native in Chinese, Fluent in English (TOEFL IBT: 104, Dec/2008) and Japanese (Level 2 certificated, 2008)