James A

James A. Toghia		Contact information available by request to toghia@usc.edu
Summary	Recently graduated with MS in Computer Engineering (Computer Architecture specialization) following 5+ years of industry experience. Currently pursuing PhD with active interest in multithreaded and parallel processing research. Open to all employment opportunities that help me realize my goal.
Skills	Pascal, C/C++, Perl, HTML, CLIPS, Assembly (Intel, Motorola, MIPS, DLX, Texas Instruments TMS320C3x DSP), VHDL/Verilog, Viewlogic, Synopsys, Magma Design Tools, Matlab, HSpice, SimpleScalar, SIMICS, FlexSim, In-target probes (ITP), Logic analyzers, Programmable logic devices (FPGAs. CPLDs), VLSI design with Magic, MS Office Suite
Education	Summer 2002 – Present	Univ. of Southern California	Los Angeles, CA
	Master of Science / Doctor of Philosophy, Computer Engineering (Emphasis in Computer Architecture) MS degree awarded May 2004 Currently maintaining 3.53 GPA Completed courses in out-of-order computer systems architecture, clusters, computer networks, digital switching (including asynchronous design), VLSI (logical effort and skew-tolerant design), real-time computing systems, MOS fabrication and characterization techniques, artificial intelligence, algorithm analysis, multiflow and multithreaded architecture, probabilistic modeling and queuing theory, fuzzy logic and neural networks, probabilistic AI, and interconnection networks Currently studying parallel computing architecture Research projects to date include the following: The design, implementation, and testing of a real-time scheduler and DSP for the acquisition, processing, and reporting of data from multiple independent probes (temperature and signal analysis) with analog signal conditioning, digital filtering (high pass, low pass, band pass), and interrupt handling (to set the status of the digital filter). The goal was to guarantee that all tasks would be serviced within a specified timeframe, and multiple scheduling algorithms (rate monotonic and least laxity nonpreemptive) were implemented on the Tern Birdbox. Power analysis and possible performance/power enhancements to the Stanford Hydra speculative multithreaded processor (in progress). The design, simulation, and comparison of token ring and distributed crossbar topologies for the implementation of on-chip interconnection networks. Developed wire model in HSpice to estimate delays and VHDL models to estimate relative logic (gate) costs. Then, developed custom queuing simulator in C to measure relative throughput and latency of each model against a wide range of parameters (network size, arrival rate, error/retransmission rate, traffic locality).
	Fall 2001 – Spring 2002	UCI Extension	Irvine, CA
	Specialized Studies Certification – Advanced Digital Systems Engineering Maintained 4.00 GPA while studying many aspects of systems’ design process: architectural definition, RTL translation, layout, and back-end design with cell libraries Completed lab activities in VHDL, Synopsys, and Magma Blast Fusion Program also included instruction on “System on chip” development
	Fall 2001 – Spring 2002	UCI Extension	Irvine, CA
	Specialized Studies Certification – Digital Signal Processing Maintained 4.00 GPA while learning DSP theories and transforms, as well as the software tools to apply them Performed DSP analysis and modeling with Matlab Developed audio flanger effect processor in assembly language for a Texas Instruments TMS320C31 DSP, as well as learned general aspects of real-time DSP design using off-the-shelf DSP components Studied principles of custom DSP ASIC development, as well as the growing trend to use FPGAs for rapid prototyping Designed and simulated an audio filter, implemented in an Altera Flex10K FPGA, using Matlab to determine the filter coefficients, and VHDL to implement the design
	Spring 2001	UCSD Extension	San Diego, CA
	Verilog Programming Earned grade of A-, while learning Verilog syntax for behavioral and structural design and simulation, as well as generally preferred coding style techniques Developed numerous logic designs, wrote testbenches, performed simulations, and synthesized logic Introduced to SystemC for the purpose of higher-level logic design from C-language models
	1993 – 1996, 1999	Univ. of Southern California	Los Angeles, CA
	Bachelor of Science, Computer Engineering/Computer Science Maintained 3.22 GPA, 3.25 in electrical engineering and computer science (Dean's List - Fall '94, Spring '95) Earned membership in Tau Beta Pi, Eta Kappa Nu, and Upsilon Pi Epsilon national honor societies
Work Experience	Aug. 2002 – May 2003	Univ. of Southern California	Los Angeles, CA
	Teaching Assistant Prepared lessons and lead discussion sections for undergraduate students studying basic computer architecture Provided assistance with lab assignments using both Viewlogic and the Motorola 68K simulator Prepared homework answer keys for the grader, graded quizes, and proctored midterm and final exams
	Mar. 2000 – June 2001	Hifn	Carlsbad, CA
	Applications Engineer Developed specifications, specification updates, and application notes to facilitate the implementation of Hifn network security processors in customer designs Actively participated in the debugging of customer hardware and software designs
	Nov. 1997 – Dec. 1999	Intel	Hillsboro, OR
	Technical Marketing Engineer Enabled customer server and workstation designs based on high-end processors and chipsets while working in the Enterprise Server Group and Performance Microprocessor Group Developed customer specifications, design guidelines, and specification updates and deliver appropriate customer communications Assisted in the debugging of customer platforms and facilitated engagement between engineering and customers Developed technology demonstrations and presented them publicly at PC Expo '98
	Jan. 1997 – Nov. 1997	Intel	Hillsboro, OR
	Technical Marketing Intern Worked in the Enterprise Server Group to enable server designs based on Pentium® II Xeon™ processors and the Intel® 450NX PCIset Resolved customer issues and participated in platform design reviews
	Jan. 1996 – Aug. 1996	Intel	Hillsboro, OR
	Validation Intern Designed automatic test generators (ATGs) for the system level simulation of the 82450GX chipset Designed C language-based DRAM simulation for the validation of the Intel 450NX chipset
References	Available upon request