I am currently pursuing Master of Science at University of Southern California (USC), Los Angeles. Being a go-getter, I’m completely fueled by Sir J.G. Holland’s quote, “God gives every bird its food, but he does not throw it into its nest.” My perspective since then has been, ‘if sought and if efforts are rightly directed, stellar results alone can be the outcome’. Such an outlook helped me achieve excellence in my areas of interest like VLSI/ASIC/RTL/Digital/Logic Design/DFT. In this regard, I am actively seeking Spring 2014 Co-op and/or Full Time opportunity in the same fields.
Graduate Engineering School Coursework at USC:
Computer Systems Organizations (EE457)
MOS VLSI Circuit Design (EE477)
Spring 2013: Computer Architecture (EE557)
VLSI System Design A (EE577A)
Solid State Processing and Integrated Circuits Laboratory (EE504)
VLSI System Design B (EE577B) (ongoing)
Diagnosis and Design of Reliable Digital Systems (EE658) (ongoing)
University of Southern California (Fall 2012 to present):
1. [VERILOG] Currently designing a synthesizable RTL based DDR2 Memory Controller that initializes, reads/writes and refreshes a Micron SDRAM using NCVerilog, Synopsys DC.
2. [VERILOG] Designed digital logics, state machines, and RTL designs for single cycle, multi cycle and pipelined versions of MIPS processor in Modelsim using Verilog.
3. [VERILOG] Designed 5-stage version of the MIPS processor using Verilog. The design incorporated an Arithmetic Logic Unit (ALU), Forwarding Unit, Hazard Detection Unit, Branch Prediction Unit, and a Stalling Unit. Used testbenches to validate and verify the pipeline systems and subsystems.
4. [ASIC VLSI DESIGN] Designing full-custom layouts and schematics of various CMOS gates, and then incorporating these to create larger functional units, such as ALU with inequality checker, multiplexers, and comparators in Cadence Virtuoso. Performing optimization, sizing, and testing/verification to ensure correct functionality.
5. [ASIC VLSI DESIGN] Designed full custom layout of Multi-Processor System-on-Chip Data Transmission Router using Bitonic Sorting Network. Compact design ensured an optimal area*delay product.
6. [ASIC VLSI DESIGN] Delay estimation of the circuit with Interconnect Capacitance using Non-Linear Delay Model (NLDM) with the help of look up table (LUT) and comparing it with the actual simulation results. Also used Perl to automate the calculation process thereby finding the propagation delay.
7. [ASIC VLSI DESIGN] Designed a fully functional and fully custom General Purpose Multi-Cycle CPU with 1KB SRAM, 16-bit RCA adder, 8-bit Multiplier and multiple registers using Cadence Virtuoso. Schematic and Layout were designed to ensure optimal area*delay product.
8. [COMPUTER ARCHITECURE] Explored the design space of a typical micro architecture enhancement to an existing processor design like Tomasulo Algorithm during EE557 Computer Architecture course.
University of Wisconsin-Madison (Jan 2011 to May 2011):
9. [VERILOG] Worked on a project of making an AUTOMATED DRINK DISPENSER using FREESCALE i.MX21 ARM9 processor.
10. [POWER ELECTRONICS] Designed a BUCK CONVERTER which satisfied the provided set of specifications.