-
From 01/2010 to 05/2010, I led a group of 4 members to design and implement a compiler
for FPGA emulation of digital circuits under the supervision of Prof. Breuer. It takes the design of a circuit represented as netlists as input.
It partitions the gates/cells and assign each of them to 1 of the 6 FPGA boards in the emulation system (partitioning). Then
it routes the nets among each FPGAs (inter-routing) and assigns the pins. Then it places each gate/cell on each FPGA to
a specific location/CLB (Placement). Finally it routes the nets within each FPGA (intra-routing). I individually finished
partitioning using modified F-M heuristics with additional parameters to improve both inter and intra routability. It produced verifiably
good results for various test cases.
Detailed project introduction and specification (pdf)
| Flow of the Compiler: |
| Partitioning |
 |
| Inter-FPGA Routing and I/O Pin Assignment |
|
| Placement |
|
| Intra-FPGA Routing |
| *interatctions among modules are not presented |
Project final design, summary, and results (pdf)
Download compiler source code (zip)
The University of Southern California does not screen or control the content on this website and thus does not guarantee the accuracy, integrity, or quality of such content. All content on this website is provided by and is the sole responsibility of the person from which such content originated, and such content does not necessarily reflect the opinions of the University administration or the Board of Trustees