Designing VLIS layout of a high speed, high dense and low power fulladder, using MORBN20 techonology in Tanner LEdit

I believe Mathematics is the mother of all Sciences including Computer Science. I learned graph theories in Discrete Mathematic course but I was really fascinated when I found its applications in VLSI system for designing layout with traversing Euler path in graphs. In a competition for designing a layout, I ranked 1st between more than 40 participants and designed the most effective layout in terms of area, delay and power consumption.

HSpice_Extracted_Code.v



* Circuit Extracted by Tanner Research's L-Edit Version 8.30 / Extract Version 8.30 ;
* Cell:  _ReadMe	Version 1.116
* Extract Definition File:  MORBN20.EXT
* Extract Date and Time:  11/15/2016 - 09:48

* Warning:  Layers with Unassigned AREA Capacitance.
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* Warning: Layers with Unassigned FRINGE Capacitance. * * * * *

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* * Warning: Layers with Zero Resistance. * * * * * NODE NAME ALIASES * 8 = a1 (521,131) * 13 = cout (757.5,66.5) * 18 = s0 (752.5,98) * 26 = a3 (730.5,59.5) * 27 = s3 (628.5,26) * 34 = b3 (722.5,59.5) * 35 = s1 (622,98) * 40 = b0 (658.5,130) * 41 = a0 (651,131.5) * 42 = cin (666.5,131.5) * 46 = b2 (593,60) * 48 = s2 (498.5,24) * 50 = VDD (625,121) * 55 = VSS (627,4.5) * 58 = a2 (600.5,60.5) * 66 = b1 (530,130.5) M1 ? b0 ? VDD PMOS L=0.1p W=0.1p * M1 DRAIN GATE SOURCE BULK (730 117.5 732 122.5) M2 3 b0 2 VDD PMOS L=2u W=5u AD=15p PD=11u AS=15p PS=11u * M2 DRAIN GATE SOURCE BULK (730 108 732 113) M3 ? cin ? VDD PMOS L=0.1p W=0.1p * M3 DRAIN GATE SOURCE BULK (738 117.5 740 122.5) M4 ? cin ? VDD PMOS L=0.1p W=0.1p * M4 DRAIN GATE SOURCE BULK (706 117.5 708 122.5) M5 3 cin VDD VDD PMOS L=2u W=5u AD=15p PD=11u AS=15p PS=11u * M5 DRAIN GATE SOURCE BULK (738 108 740 113) M6 1 cin VDD VDD PMOS L=2u W=5u AD=15p PD=11u AS=15p PS=11u * M6 DRAIN GATE SOURCE BULK (706 108 708 113) M7 ? a0 ? VDD PMOS L=0.1p W=0.1p * M7 DRAIN GATE SOURCE BULK (722 117.5 724 122.5) M8 2 a0 19 VDD PMOS L=2u W=5u AD=15p PD=11u AS=15p PS=11u * M8 DRAIN GATE SOURCE BULK (722 108 724 113) M9 s0 19 VDD VDD PMOS L=2u W=5u AD=27.5p PD=21u AS=15p PS=11u * M9 DRAIN GATE SOURCE BULK (746 108 748 113) M10 19 23 1 VDD PMOS L=2u W=5u AD=15p PD=11u AS=15p PS=11u * M10 DRAIN GATE SOURCE BULK (714 108 716 113) M11 ? b0 ? VDD PMOS L=0.1p W=0.1p * M11 DRAIN GATE SOURCE BULK (698 117.5 700 122.5) M12 VDD b0 1 VDD PMOS L=2u W=5u AD=15p PD=11u AS=16.25p PS=11.5u * M12 DRAIN GATE SOURCE BULK (698 108 700 113) M13 ? b1 ? VDD PMOS L=0.1p W=0.1p * M13 DRAIN GATE SOURCE BULK (601 117.5 603 122.5) M14 5 b1 4 VDD PMOS L=2u W=5u AD=15p PD=11u AS=15p PS=11u * M14 DRAIN GATE SOURCE BULK (601 108 603 113) M15 ? 67 ? VDD PMOS L=0.1p W=0.1p * M15 DRAIN GATE SOURCE BULK (609 117.5 611 122.5) M16 5 67 VDD VDD PMOS L=2u W=5u AD=15p PD=11u AS=15p PS=11u * M16 DRAIN GATE SOURCE BULK (609 108 611 113) M17 ? a1 ? VDD PMOS L=0.1p W=0.1p * M17 DRAIN GATE SOURCE BULK (593 117.5 595 122.5) M18 4 a1 54 VDD PMOS L=2u W=5u AD=15p PD=11u AS=15p PS=11u * M18 DRAIN GATE SOURCE BULK (593 108 595 113) M19 s1 54 VDD VDD PMOS L=2u W=5u AD=27.5p PD=21u AS=15p PS=11u * M19 DRAIN GATE SOURCE BULK (617 108 619 113) M20 ? cin ? VDD PMOS L=0.1p W=0.1p * M20 DRAIN GATE SOURCE BULK (665.5 117.5 667.5 122.5) M21 23 cin 7 VDD PMOS L=2u W=5u AD=15p PD=11u AS=15p PS=11u * M21 DRAIN GATE SOURCE BULK (665.5 108 667.5 113) M22 VDD 23 67 VDD PMOS L=2u W=5u AD=27.5p PD=21u AS=30p PS=22u * M22 DRAIN GATE SOURCE BULK (633.5 108 635.5 113) M23 ? a0 ? VDD PMOS L=0.1p W=0.1p * M23 DRAIN GATE SOURCE BULK (689.5 117.5 691.5 122.5) M24 VDD a0 1 VDD PMOS L=2u W=5u AD=15p PD=11u AS=16.25p PS=11.5u * M24 DRAIN GATE SOURCE BULK (689.5 108 691.5 113) M25 ? a0 ? VDD PMOS L=0.1p W=0.1p * M25 DRAIN GATE SOURCE BULK (673.5 117.5 675.5 122.5) M26 6 a0 23 VDD PMOS L=2u W=5u AD=15p PD=11u AS=15p PS=11u * M26 DRAIN GATE SOURCE BULK (673.5 108 675.5 113) M27 ? a0 ? VDD PMOS L=0.1p W=0.1p * M27 DRAIN GATE SOURCE BULK (649.5 117.5 651.5 122.5) M28 VDD a0 7 VDD PMOS L=2u W=5u AD=15p PD=11u AS=27.5p PS=21u * M28 DRAIN GATE SOURCE BULK (649.5 108 651.5 113) M29 ? b0 ? VDD PMOS L=0.1p W=0.1p * M29 DRAIN GATE SOURCE BULK (681.5 117.5 683.5 122.5) M30 VDD b0 6 VDD PMOS L=2u W=5u AD=15p PD=11u AS=15p PS=11u * M30 DRAIN GATE SOURCE BULK (681.5 108 683.5 113) M31 ? b0 ? VDD PMOS L=0.1p W=0.1p * M31 DRAIN GATE SOURCE BULK (657.5 117.5 659.5 122.5) M32 7 b0 VDD VDD PMOS L=2u W=5u AD=15p PD=11u AS=15p PS=11u * M32 DRAIN GATE SOURCE BULK (657.5 108 659.5 113) M33 ? 67 ? VDD PMOS L=0.1p W=0.1p * M33 DRAIN GATE SOURCE BULK (577 117.5 579 122.5) M34 ? 67 ? VDD PMOS L=0.1p W=0.1p * M34 DRAIN GATE SOURCE BULK (536.5 117.5 538.5 122.5) M35 9 67 VDD VDD PMOS L=2u W=5u AD=15p PD=11u AS=15p PS=11u * M35 DRAIN GATE SOURCE BULK (577 108 579 113) M36 44 67 11 VDD PMOS L=2u W=5u AD=15p PD=11u AS=15p PS=11u * M36 DRAIN GATE SOURCE BULK (536.5 108 538.5 113) M37 VDD 44 45 VDD PMOS L=2u W=5u AD=27.5p PD=21u AS=30p PS=22u * M37 DRAIN GATE SOURCE BULK (504.5 108 506.5 113) M38 ? a1 ? VDD PMOS L=0.1p W=0.1p * M38 DRAIN GATE SOURCE BULK (560.5 117.5 562.5 122.5) M39 9 a1 VDD VDD PMOS L=2u W=5u AD=16.25p PD=11.5u AS=15p PS=11u * M39 DRAIN GATE SOURCE BULK (560.5 108 562.5 113) M40 ? a1 ? VDD PMOS L=0.1p W=0.1p * M40 DRAIN GATE SOURCE BULK (544.5 117.5 546.5 122.5) M41 10 a1 44 VDD PMOS L=2u W=5u AD=15p PD=11u AS=15p PS=11u * M41 DRAIN GATE SOURCE BULK (544.5 108 546.5 113) M42 ? a1 ? VDD PMOS L=0.1p W=0.1p * M42 DRAIN GATE SOURCE BULK (520.5 117.5 522.5 122.5) M43 VDD a1 11 VDD PMOS L=2u W=5u AD=15p PD=11u AS=27.5p PS=21u * M43 DRAIN GATE SOURCE BULK (520.5 108 522.5 113) M44 54 44 9 VDD PMOS L=2u W=5u AD=15p PD=11u AS=15p PS=11u * M44 DRAIN GATE SOURCE BULK (585 108 587 113) M45 ? b1 ? VDD PMOS L=0.1p W=0.1p * M45 DRAIN GATE SOURCE BULK (552.5 117.5 554.5 122.5) M46 VDD b1 10 VDD PMOS L=2u W=5u AD=15p PD=11u AS=15p PS=11u * M46 DRAIN GATE SOURCE BULK (552.5 108 554.5 113) M47 ? b1 ? VDD PMOS L=0.1p W=0.1p * M47 DRAIN GATE SOURCE BULK (528.5 117.5 530.5 122.5) M48 11 b1 VDD VDD PMOS L=2u W=5u AD=15p PD=11u AS=15p PS=11u * M48 DRAIN GATE SOURCE BULK (528.5 108 530.5 113) M49 ? b1 ? VDD PMOS L=0.1p W=0.1p * M49 DRAIN GATE SOURCE BULK (569 117.5 571 122.5) M50 VDD b1 9 VDD PMOS L=2u W=5u AD=15p PD=11u AS=16.25p PS=11.5u * M50 DRAIN GATE SOURCE BULK (569 108 571 113) M51 ? 24 ? VDD PMOS L=0.1p W=0.1p * M51 DRAIN GATE SOURCE BULK (713 46.5 715 51.5) M52 16 24 22 VDD PMOS L=2u W=5u AD=15p PD=11u AS=15p PS=11u * M52 DRAIN GATE SOURCE BULK (713 37 715 42) M53 cout 22 VDD VDD PMOS L=2u W=5u AD=30p PD=22u AS=27.5p PS=21u * M53 DRAIN GATE SOURCE BULK (745 37 747 42) M54 ? a3 ? VDD PMOS L=0.1p W=0.1p * M54 DRAIN GATE SOURCE BULK (705 46.5 707 51.5) M55 22 a3 15 VDD PMOS L=2u W=5u AD=15p PD=11u AS=15p PS=11u * M55 DRAIN GATE SOURCE BULK (705 37 707 42) M56 ? a3 ? VDD PMOS L=0.1p W=0.1p * M56 DRAIN GATE SOURCE BULK (729 46.5 731 51.5) M57 16 a3 VDD VDD PMOS L=2u W=5u AD=27.5p PD=21u AS=15p PS=11u * M57 DRAIN GATE SOURCE BULK (729 37 731 42) M58 ? b3 ? VDD PMOS L=0.1p W=0.1p * M58 DRAIN GATE SOURCE BULK (697 46.5 699 51.5) M59 15 b3 VDD VDD PMOS L=2u W=5u AD=15p PD=11u AS=15p PS=11u * M59 DRAIN GATE SOURCE BULK (697 37 699 42) M60 ? b3 ? VDD PMOS L=0.1p W=0.1p * M60 DRAIN GATE SOURCE BULK (721 46.5 723 51.5) M61 VDD b3 16 VDD PMOS L=2u W=5u AD=15p PD=11u AS=15p PS=11u * M61 DRAIN GATE SOURCE BULK (721 37 723 42) M62 12 24 22 VSS NMOS L=2u W=5u AD=15p PD=11u AS=15p PS=11u * M62 DRAIN GATE SOURCE BULK (713 11 715 16) M63 cout 22 VSS VSS NMOS L=2u W=5u AD=30p PD=22u AS=27.5p PS=21u * M63 DRAIN GATE SOURCE BULK (745 11 747 16) M64 22 a3 14 VSS NMOS L=2u W=5u AD=15p PD=11u AS=15p PS=11u * M64 DRAIN GATE SOURCE BULK (705 11 707 16) M65 12 a3 VSS VSS NMOS L=2u W=5u AD=27.5p PD=21u AS=15p PS=11u * M65 DRAIN GATE SOURCE BULK (729 11 731 16) M66 14 b3 VSS VSS NMOS L=2u W=5u AD=15p PD=11u AS=15p PS=11u * M66 DRAIN GATE SOURCE BULK (697 11 699 16) M67 VSS b3 12 VSS NMOS L=2u W=5u AD=15p PD=11u AS=15p PS=11u * M67 DRAIN GATE SOURCE BULK (721 11 723 16) M68 21 b0 20 VSS NMOS L=2u W=5u AD=15p PD=11u AS=15p PS=11u * M68 DRAIN GATE SOURCE BULK (730 82 732 87) M69 VSS cin 21 VSS NMOS L=2u W=5u AD=15p PD=11u AS=15p PS=11u * M69 DRAIN GATE SOURCE BULK (738 82 740 87) M70 17 cin VSS VSS NMOS L=2u W=5u AD=15p PD=11u AS=15p PS=11u * M70 DRAIN GATE SOURCE BULK (706 82 708 87) M71 20 a0 19 VSS NMOS L=2u W=5u AD=15p PD=11u AS=15p PS=11u * M71 DRAIN GATE SOURCE BULK (722 82 724 87) M72 s0 19 VSS VSS NMOS L=2u W=5u AD=27.5p PD=21u AS=15p PS=11u * M72 DRAIN GATE SOURCE BULK (746 82 748 87) M73 19 23 17 VSS NMOS L=2u W=5u AD=15p PD=11u AS=15p PS=11u * M73 DRAIN GATE SOURCE BULK (714 82 716 87) M74 VSS b0 17 VSS NMOS L=2u W=5u AD=15p PD=11u AS=16.25p PS=11.5u * M74 DRAIN GATE SOURCE BULK (698 82 700 87) M75 ? b3 ? VDD PMOS L=0.1p W=0.1p * M75 DRAIN GATE SOURCE BULK (648.5 46.5 650.5 51.5) M76 32 b3 33 VDD PMOS L=2u W=5u AD=15p PD=11u AS=15p PS=11u * M76 DRAIN GATE SOURCE BULK (648.5 37 650.5 42) M77 ? 24 ? VDD PMOS L=0.1p W=0.1p * M77 DRAIN GATE SOURCE BULK (672.5 46.5 674.5 51.5) M78 ? 24 ? VDD PMOS L=0.1p W=0.1p * M78 DRAIN GATE SOURCE BULK (640.5 46.5 642.5 51.5) M79 VDD 24 31 VDD PMOS L=2u W=5u AD=15p PD=11u AS=15p PS=11u * M79 DRAIN GATE SOURCE BULK (672.5 37 674.5 42) M80 33 24 VDD VDD PMOS L=2u W=5u AD=15p PD=11u AS=15p PS=11u * M80 DRAIN GATE SOURCE BULK (640.5 37 642.5 42) M81 ? a3 ? VDD PMOS L=0.1p W=0.1p * M81 DRAIN GATE SOURCE BULK (656.5 46.5 658.5 51.5) M82 28 a3 32 VDD PMOS L=2u W=5u AD=15p PD=11u AS=15p PS=11u * M82 DRAIN GATE SOURCE BULK (656.5 37 658.5 42) M83 ? a3 ? VDD PMOS L=0.1p W=0.1p * M83 DRAIN GATE SOURCE BULK (689 46.5 691 51.5) M84 31 a3 VDD VDD PMOS L=2u W=5u AD=16.25p PD=11.5u AS=15p PS=11u * M84 DRAIN GATE SOURCE BULK (689 37 691 42) M85 VDD 28 s3 VDD PMOS L=2u W=5u AD=15p PD=11u AS=27.5p PS=21u * M85 DRAIN GATE SOURCE BULK (632.5 37 634.5 42) M86 31 22 28 VDD PMOS L=2u W=5u AD=15p PD=11u AS=15p PS=11u * M86 DRAIN GATE SOURCE BULK (664.5 37 666.5 42) M87 ? b3 ? VDD PMOS L=0.1p W=0.1p * M87 DRAIN GATE SOURCE BULK (680.5 46.5 682.5 51.5) M88 31 b3 VDD VDD PMOS L=2u W=5u AD=16.25p PD=11.5u AS=15p PS=11u * M88 DRAIN GATE SOURCE BULK (680.5 37 682.5 42) M89 24 43 VDD VDD PMOS L=2u W=5u AD=30p PD=22u AS=27.5p PS=21u * M89 DRAIN GATE SOURCE BULK (616 37 618 42) M90 ? a2 ? VDD PMOS L=0.1p W=0.1p * M90 DRAIN GATE SOURCE BULK (600 46.5 602 51.5) M91 51 a2 VDD VDD PMOS L=2u W=5u AD=27.5p PD=21u AS=15p PS=11u * M91 DRAIN GATE SOURCE BULK (600 37 602 42) M92 ? b2 ? VDD PMOS L=0.1p W=0.1p * M92 DRAIN GATE SOURCE BULK (592 46.5 594 51.5) M93 VDD b2 51 VDD PMOS L=2u W=5u AD=15p PD=11u AS=15p PS=11u * M93 DRAIN GATE SOURCE BULK (592 37 594 42) M94 29 b3 30 VSS NMOS L=2u W=5u AD=15p PD=11u AS=15p PS=11u * M94 DRAIN GATE SOURCE BULK (648.5 11 650.5 16) M95 VSS 24 25 VSS NMOS L=2u W=5u AD=15p PD=11u AS=15p PS=11u * M95 DRAIN GATE SOURCE BULK (672.5 11 674.5 16) M96 30 24 VSS VSS NMOS L=2u W=5u AD=15p PD=11u AS=15p PS=11u * M96 DRAIN GATE SOURCE BULK (640.5 11 642.5 16) M97 28 a3 29 VSS NMOS L=2u W=5u AD=15p PD=11u AS=15p PS=11u * M97 DRAIN GATE SOURCE BULK (656.5 11 658.5 16) M98 25 a3 VSS VSS NMOS L=2u W=5u AD=16.25p PD=11.5u AS=15p PS=11u * M98 DRAIN GATE SOURCE BULK (689 11 691 16) M99 VSS 28 s3 VSS NMOS L=2u W=5u AD=15p PD=11u AS=27.5p PS=21u * M99 DRAIN GATE SOURCE BULK (632.5 11 634.5 16) M100 25 22 28 VSS NMOS L=2u W=5u AD=15p PD=11u AS=15p PS=11u * M100 DRAIN GATE SOURCE BULK (664.5 11 666.5 16) M101 25 b3 VSS VSS NMOS L=2u W=5u AD=16.25p PD=11.5u AS=15p PS=11u * M101 DRAIN GATE SOURCE BULK (680.5 11 682.5 16) M102 24 43 VSS VSS NMOS L=2u W=5u AD=30p PD=22u AS=27.5p PS=21u * M102 DRAIN GATE SOURCE BULK (616 11 618 16) M103 37 b1 36 VSS NMOS L=2u W=5u AD=15p PD=11u AS=15p PS=11u * M103 DRAIN GATE SOURCE BULK (601 82 603 87) M104 VSS 67 37 VSS NMOS L=2u W=5u AD=15p PD=11u AS=15p PS=11u * M104 DRAIN GATE SOURCE BULK (609 82 611 87) M105 36 a1 54 VSS NMOS L=2u W=5u AD=15p PD=11u AS=15p PS=11u * M105 DRAIN GATE SOURCE BULK (593 82 595 87) M106 s1 54 VSS VSS NMOS L=2u W=5u AD=27.5p PD=21u AS=15p PS=11u * M106 DRAIN GATE SOURCE BULK (617 82 619 87) M107 23 cin 38 VSS NMOS L=2u W=5u AD=15p PD=11u AS=15p PS=11u * M107 DRAIN GATE SOURCE BULK (665.5 82 667.5 87) M108 VSS 23 67 VSS NMOS L=2u W=5u AD=27.5p PD=21u AS=30p PS=22u * M108 DRAIN GATE SOURCE BULK (633.5 82 635.5 87) M109 VSS a0 17 VSS NMOS L=2u W=5u AD=15p PD=11u AS=16.25p PS=11.5u * M109 DRAIN GATE SOURCE BULK (689.5 82 691.5 87) M110 39 a0 23 VSS NMOS L=2u W=5u AD=15p PD=11u AS=15p PS=11u * M110 DRAIN GATE SOURCE BULK (673.5 82 675.5 87) M111 VSS a0 38 VSS NMOS L=2u W=5u AD=15p PD=11u AS=27.5p PS=21u * M111 DRAIN GATE SOURCE BULK (649.5 82 651.5 87) M112 VSS b0 39 VSS NMOS L=2u W=5u AD=15p PD=11u AS=15p PS=11u * M112 DRAIN GATE SOURCE BULK (681.5 82 683.5 87) M113 38 b0 VSS VSS NMOS L=2u W=5u AD=15p PD=11u AS=15p PS=11u * M113 DRAIN GATE SOURCE BULK (657.5 82 659.5 87) M114 47 a2 VSS VSS NMOS L=2u W=5u AD=27.5p PD=21u AS=15p PS=11u * M114 DRAIN GATE SOURCE BULK (600 11 602 16) M115 VSS b2 47 VSS NMOS L=2u W=5u AD=15p PD=11u AS=15p PS=11u * M115 DRAIN GATE SOURCE BULK (592 11 594 16) M116 VDD 49 s2 VDD PMOS L=2u W=5u AD=15p PD=11u AS=27.5p PS=21u * M116 DRAIN GATE SOURCE BULK (503.5 37 505.5 42) M117 ? b2 ? VDD PMOS L=0.1p W=0.1p * M117 DRAIN GATE SOURCE BULK (519.5 46.5 521.5 51.5) M118 63 b2 64 VDD PMOS L=2u W=5u AD=15p PD=11u AS=15p PS=11u * M118 DRAIN GATE SOURCE BULK (519.5 37 521.5 42) M119 ? 45 ? VDD PMOS L=0.1p W=0.1p * M119 DRAIN GATE SOURCE BULK (584 46.5 586 51.5) M120 ? 45 ? VDD PMOS L=0.1p W=0.1p * M120 DRAIN GATE SOURCE BULK (543.5 46.5 545.5 51.5) M121 ? 45 ? VDD PMOS L=0.1p W=0.1p * M121 DRAIN GATE SOURCE BULK (511.5 46.5 513.5 51.5) M122 51 45 43 VDD PMOS L=2u W=5u AD=15p PD=11u AS=15p PS=11u * M122 DRAIN GATE SOURCE BULK (584 37 586 42) M123 VDD 45 62 VDD PMOS L=2u W=5u AD=15p PD=11u AS=15p PS=11u * M123 DRAIN GATE SOURCE BULK (543.5 37 545.5 42) M124 64 45 VDD VDD PMOS L=2u W=5u AD=15p PD=11u AS=15p PS=11u * M124 DRAIN GATE SOURCE BULK (511.5 37 513.5 42) M125 ? a2 ? VDD PMOS L=0.1p W=0.1p * M125 DRAIN GATE SOURCE BULK (527.5 46.5 529.5 51.5) M126 49 a2 63 VDD PMOS L=2u W=5u AD=15p PD=11u AS=15p PS=11u * M126 DRAIN GATE SOURCE BULK (527.5 37 529.5 42) M127 ? a2 ? VDD PMOS L=0.1p W=0.1p * M127 DRAIN GATE SOURCE BULK (560 46.5 562 51.5) M128 VDD a2 62 VDD PMOS L=2u W=5u AD=15p PD=11u AS=16.25p PS=11.5u * M128 DRAIN GATE SOURCE BULK (560 37 562 42) M129 ? a2 ? VDD PMOS L=0.1p W=0.1p * M129 DRAIN GATE SOURCE BULK (576 46.5 578 51.5) M130 43 a2 65 VDD PMOS L=2u W=5u AD=15p PD=11u AS=15p PS=11u * M130 DRAIN GATE SOURCE BULK (576 37 578 42) M131 62 43 49 VDD PMOS L=2u W=5u AD=15p PD=11u AS=15p PS=11u * M131 DRAIN GATE SOURCE BULK (535.5 37 537.5 42) M132 ? b2 ? VDD PMOS L=0.1p W=0.1p * M132 DRAIN GATE SOURCE BULK (568 46.5 570 51.5) M133 65 b2 VDD VDD PMOS L=2u W=5u AD=15p PD=11u AS=15p PS=11u * M133 DRAIN GATE SOURCE BULK (568 37 570 42) M134 ? b2 ? VDD PMOS L=0.1p W=0.1p * M134 DRAIN GATE SOURCE BULK (551.5 46.5 553.5 51.5) M135 62 b2 VDD VDD PMOS L=2u W=5u AD=16.25p PD=11.5u AS=15p PS=11u * M135 DRAIN GATE SOURCE BULK (551.5 37 553.5 42) M136 VSS 49 s2 VSS NMOS L=2u W=5u AD=15p PD=11u AS=27.5p PS=21u * M136 DRAIN GATE SOURCE BULK (503.5 11 505.5 16) M137 52 67 VSS VSS NMOS L=2u W=5u AD=15p PD=11u AS=15p PS=11u * M137 DRAIN GATE SOURCE BULK (577 82 579 87) M138 44 67 53 VSS NMOS L=2u W=5u AD=15p PD=11u AS=15p PS=11u * M138 DRAIN GATE SOURCE BULK (536.5 82 538.5 87) M139 VSS 44 45 VSS NMOS L=2u W=5u AD=27.5p PD=21u AS=30p PS=22u * M139 DRAIN GATE SOURCE BULK (504.5 82 506.5 87) M140 52 a1 VSS VSS NMOS L=2u W=5u AD=16.25p PD=11.5u AS=15p PS=11u * M140 DRAIN GATE SOURCE BULK (560.5 82 562.5 87) M141 56 a1 44 VSS NMOS L=2u W=5u AD=15p PD=11u AS=15p PS=11u * M141 DRAIN GATE SOURCE BULK (544.5 82 546.5 87) M142 VSS a1 53 VSS NMOS L=2u W=5u AD=15p PD=11u AS=27.5p PS=21u * M142 DRAIN GATE SOURCE BULK (520.5 82 522.5 87) M143 54 44 52 VSS NMOS L=2u W=5u AD=15p PD=11u AS=15p PS=11u * M143 DRAIN GATE SOURCE BULK (585 82 587 87) M144 VSS b1 56 VSS NMOS L=2u W=5u AD=15p PD=11u AS=15p PS=11u * M144 DRAIN GATE SOURCE BULK (552.5 82 554.5 87) M145 53 b1 VSS VSS NMOS L=2u W=5u AD=15p PD=11u AS=15p PS=11u * M145 DRAIN GATE SOURCE BULK (528.5 82 530.5 87) M146 VSS b1 52 VSS NMOS L=2u W=5u AD=15p PD=11u AS=16.25p PS=11.5u * M146 DRAIN GATE SOURCE BULK (569 82 571 87) M147 59 b2 60 VSS NMOS L=2u W=5u AD=15p PD=11u AS=15p PS=11u * M147 DRAIN GATE SOURCE BULK (519.5 11 521.5 16) M148 47 45 43 VSS NMOS L=2u W=5u AD=15p PD=11u AS=15p PS=11u * M148 DRAIN GATE SOURCE BULK (584 11 586 16) M149 VSS 45 57 VSS NMOS L=2u W=5u AD=15p PD=11u AS=15p PS=11u * M149 DRAIN GATE SOURCE BULK (543.5 11 545.5 16) M150 60 45 VSS VSS NMOS L=2u W=5u AD=15p PD=11u AS=15p PS=11u * M150 DRAIN GATE SOURCE BULK (511.5 11 513.5 16) M151 49 a2 59 VSS NMOS L=2u W=5u AD=15p PD=11u AS=15p PS=11u * M151 DRAIN GATE SOURCE BULK (527.5 11 529.5 16) M152 VSS a2 57 VSS NMOS L=2u W=5u AD=15p PD=11u AS=16.25p PS=11.5u * M152 DRAIN GATE SOURCE BULK (560 11 562 16) M153 43 a2 61 VSS NMOS L=2u W=5u AD=15p PD=11u AS=15p PS=11u * M153 DRAIN GATE SOURCE BULK (576 11 578 16) M154 57 43 49 VSS NMOS L=2u W=5u AD=15p PD=11u AS=15p PS=11u * M154 DRAIN GATE SOURCE BULK (535.5 11 537.5 16) M155 61 b2 VSS VSS NMOS L=2u W=5u AD=15p PD=11u AS=15p PS=11u * M155 DRAIN GATE SOURCE BULK (568 11 570 16) M156 57 b2 VSS VSS NMOS L=2u W=5u AD=16.25p PD=11.5u AS=15p PS=11u * M156 DRAIN GATE SOURCE BULK (551.5 11 553.5 16) * Total Nodes: 67 * Total Elements: 156 * Total Number of Shorted Elements not written to the SPICE file: 0 * Extract Elapsed Time: 0 seconds .MODEL NMOS NMOS .MODEL PMOS PMOS .param t = 2p .param vdd = 5 .param vdd_1 = 5 .param vddval = 5 .param vdd_1val = 5 v_vdd VDD GND 5 v_vss VSS GND 0 *1 - 1 - 0 - 0 - 1 - 1 VA0 A0 0 PWL 0n 0, '3n-t' 0, 3n VddVal, '400n-t' VddVal, 400n 0, '800n-t' 0, 800n VddVal, 1200n VddVal *1 - 1 - 0 - 0 - 1 - 0 VB0 B0 0 PWL 0n 0, '200n-t' 0, 200n VddVal, '400n-t' VddVal, 400n 0, '600n-t' 0, 600n VddVal, '1000n-t' VddVal, 1000n 0, 1200n 0 *1 - 1 - 0 - 1 - 0 - 1 VA1 A1 0 PWL 0n 0, '3n-t' 0, 3n VddVal, '400n-t' VddVal, 400n 0, '600n-t' 0, 600n VddVal, '800n-t' VddVal, 800n 0, '1000n-t' 0, 1000n VddVal, 1200n VddVal *0 - 1 - 0 - 0 - 0 - 0 VB1 B1 0 PWL 0n 0, 1200n *1 - 1 - 0 - 1 - 0 - 0 VA2 A2 0 PWL 0n 0, '3n-t' 0, 3n VddVal, '400n-t' VddVal, 400n 0, '600n-t' 0, 600n VddVal, '800n-t' VddVal, 800n 0, 1200n 0 *0 - 1 - 0 - 0 - 1 - 1 VB2 B2 0 PWL 0n 0, 1200n *1 - 1 - 0 - 1 - 1 - 1 VA3 A3 0 PWL 0n 0, '3n-t' 0, 3n VddVal, '400n-t' VddVal, 400n 0, '600n-t' 0, 600n VddVal, 1200n VddVal *0 - 1 - 0 - 1 - 1 - 0 VB3 B3 0 PWL 0n 0, 1200n .tran 0.00001n 1200n 0 Vcin cin 0 PWL 0n 0, 1200n ************** Help Measure Commmnad ************** ******** measure tran tpsh0 trig V(A0) td= 2.9n val= 'VddVal/2' rise=1 targV(sum3) td=9n Val = 'VddVal/2' fall=1 ******* نکته ی مهم در این دستور td است. به وسیله ی td مبدا شمردن rise و fall را تعیین میکنید. برای مثال در این دستور، زمان ثبت شده اولین rise ی میباشد که بعد از 2.9 نانو ثانیه اتفاق افتاده است. ***************************************************** .measure tran tpsh0 trig V(B0) td= 190n val= 'VddVal/2' rise=1 targ V(cout) td=190n Val = 'VddVal/2' rise=1 .measure tran tpsh1 trig V(B1) td= 199n val= 'VddVal/2' rise=1 targ V(s3) td=200n Val = 'VddVal/2' rise=1 .measure tran tpsl0 trig V(B0) td= 399n val= 'VddVal/2' fall=1 targ V(s3) td=400n Val = 'VddVal/2' fall=1 .measure tran tpsl1 trig V(B0) td= 999n val= 'VddVal/2' fall=1 targ V(s3) td=1007 Val = 'VddVal/2' rise=1 .measure tran SumMaxDelay param='max(tpsh0,max(tpsh1,max(tpsl0,tpsl1)))' .measure tran tpch0 trig V(A0) td= 2.9n val= 'VddVal/2' rise=1 targ V(cout) td=2.9n Val = 'VddVal/2' rise=1 .measure tran tpch1 trig V(A1) td= 599n val= 'VddVal/2' rise=1 targ V(cout) td=600n Val = 'VddVal/2' rise=1 .measure tran tpcl0 trig V(B0) td= 399n val= 'VddVal/2' fall=1 targ V(cout) td=400n Val = 'VddVal/2' fall=1 .measure tran tpcl1 trig V(B0) td= 999n val= 'VddVal/2' fall=1 targ V(cout) td=1007 Val = 'VddVal/2' fall=1 .measure tran CoutMaxDelay param='max(tpch0,max(tpch1,max(tpcl0,tpcl1)))' .measure tran power avg power from=0n to 1200n .END