Genetic Algorithm Processor (GAP)

I have designed a customized processor for achieving a specific performance of Genetic Algorithm computational tasks. The most important feature of this system is flexibility of datapath and controller which is prepared by applying innovative hardware/software co-design techniques. It can be used easily for wide range of problems with different evaluation functions, for instance in cryptography problems, artificial intelligence problems and etc. Finally we are working on optimizing the power consumption as well as extending the system in a more general purpose.

Core_GA.sv


//!TODO: SEEDS must get from serial initialization
//!TODO: in order to place this design in my fpga with 5000 LETs, I must to use ram for first generation initialization keys.
module Core_GA(input clk, input rx, output tx);// define other input & outputs here

	parameter MAX_GEN = 1;
	
	reg [5:0] counter1;
	
	reg[7:0] tx_byte;
	reg transmit;		
		
	wire [7:0] rx_byte;
	
	wire	received;		
	wire 	is_transmitting;
	wire  	is_receiving;
	wire  	recv_error;	
			
	uart uart(					
			.clk	(clk), // The master clock for this module
			.rst	(0), // Synchronous reset.
			.rx		(rx), // Incoming serial line
			.tx		(tx), // Outgoing serial line
			.transmit (transmit), // Signal to transmit
			.tx_byte  (tx_byte), // Byte to transmit
			.received	(received), // Indicated that a byte has been received.
			.rx_byte	(rx_byte), // Byte received
			.is_receiving	(is_receiving), // Low when receive line is idle.
			.is_transmitting (is_transmitting), // Low when transmit line is idle.
			.recv_error		(recv_error) // Indicates error in receiving packet.
	 	 );			
			
	byte SEED1;
	reg lfsr1_reset;
	wire lfsr1_en;	
	byte lfsr1_out;									

	LFSR lfsr1(clk, lfsr1_reset, lfsr1_en, SEED1, lfsr1_out);	
				
	byte SEED2;
	wire lfsr2_en;
	byte lfsr2_out;	
	reg lfsr2_reset;									

	LFSR2 lfsr2(clk, lfsr2_reset, lfsr2_en, SEED2, lfsr2_out);			
	
	byte SEED3;
	wire lfsr3_en;
	byte lfsr3_out;	
	reg lfsr3_reset;									

	LFSR2 lfsr3(clk, lfsr3_reset, lfsr3_en, SEED3, lfsr3_out);						

	reg OneGen_nrst, OneGen_start, OneGen_done;
	reg [3:0] keys[0:31][0:15];			
	wire [3:0] mkeys[0:31][0:15]; 	
	
	OneGeneration oneGeneration(clk, OneGen_nrst, OneGen_start,	OneGen_done,		
						lfsr1_en, lfsr1_out,		
						lfsr2_en, lfsr2_out,		
						lfsr3_en, lfsr3_out,		
						keys, 
						mkeys
	);		
	
	reg [9:0] counter;

	reg [4:0] next_s;
	parameter INIT = 0; 
	
	initial begin						
		next_s = INIT;				
	end
	
	always @(posedge clk) begin			
	
		case(next_s)
		
	   /*0*/INIT: begin							
				if(received == 1) 
					next_s = 5;								
			end			
		
			5:begin
				SEED1 = rx_byte; // echo recived message to serial												
				next_s = 6;
			end
			
			6:begin
				if(received == 1) 
					next_s = 7;
			end
			
			7:begin
				SEED2 = rx_byte; // echo recived message to serial												
				next_s = 8;			
			end
			
			8:begin
				if(received == 1) 
					next_s = 9;
			end
			
			9:begin
				SEED3 = rx_byte; // echo recived message to serial												

				counter = 0;					
				OneGen_nrst = 0;
				lfsr1_reset = 1;				
				lfsr2_reset = 1;
				lfsr3_reset = 1;
				
				keys[0][0] = 0;keys[0][1] = 14;keys[0][2] = 13;keys[0][3] = 11;keys[0][4] = 7;keys[0][5] = 12;keys[0][6] = 9;keys[0][7] = 2;keys[0][8] = 4;keys[0][9] = 8;keys[0][10] = 15;keys[0][11] = 1;keys[0][12] = 5;keys[0][13] = 10;keys[0][14] = 3;keys[0][15] = 6;keys[1][0] = 7;keys[1][1] = 3;keys[1][2] = 5;keys[1][3] = 2;keys[1][4] = 1;keys[1][5] = 0;keys[1][6] = 9;keys[1][7] = 10;keys[1][8] = 14;keys[1][9] = 15;keys[1][10] = 11;keys[1][11] = 13;keys[1][12] = 4;keys[1][13] = 8;keys[1][14] = 12;keys[1][15] = 6;keys[2][0] = 4;keys[2][1] = 8;keys[2][2] = 1;keys[2][3] = 3;keys[2][4] = 7;keys[2][5] = 14;keys[2][6] = 13;keys[2][7] = 11;keys[2][8] = 6;keys[2][9] = 12;keys[2][10] = 0;keys[2][11] = 9;keys[2][12] = 2;keys[2][13] = 5;keys[2][14] = 10;keys[2][15] = 15;keys[3][0] = 13;keys[3][1] = 10;keys[3][2] = 4;keys[3][3] = 8;keys[3][4] = 0;keys[3][5] = 1;keys[3][6] = 2;keys[3][7] = 3;keys[3][8] = 6;keys[3][9] = 11;keys[3][10] = 5;keys[3][11] = 9;keys[3][12] = 12;keys[3][13] = 7;keys[3][14] = 14;keys[3][15] = 15;keys[4][0] = 5;keys[4][1] = 4;keys[4][2] = 13;keys[4][3] = 10;keys[4][4] = 14;keys[4][5] = 9;keys[4][6] = 2;keys[4][7] = 3;keys[4][8] = 6;keys[4][9] = 12;keys[4][10] = 8;keys[4][11] = 0;keys[4][12] = 1;keys[4][13] = 7;keys[4][14] = 11;keys[4][15] = 15;keys[5][0] = 11;keys[5][1] = 6;keys[5][2] = 12;keys[5][3] = 8;keys[5][4] = 0;keys[5][5] = 1;keys[5][6] = 2;keys[5][7] = 5;keys[5][8] = 7;keys[5][9] = 14;keys[5][10] = 3;keys[5][11] = 13;keys[5][12] = 15;keys[5][13] = 9;keys[5][14] = 10;keys[5][15] = 4;keys[6][0] = 8;keys[6][1] = 1;keys[6][2] = 2;keys[6][3] = 4;keys[6][4] = 9;keys[6][5] = 3;keys[6][6] = 7;keys[6][7] = 15;keys[6][8] = 14;keys[6][9] = 13;keys[6][10] = 10;keys[6][11] = 5;keys[6][12] = 11;keys[6][13] = 12;keys[6][14] = 0;keys[6][15] = 6;keys[7][0] = 13;keys[7][1] = 11;keys[7][2] = 7;keys[7][3] = 15;keys[7][4] = 14;keys[7][5] = 12;keys[7][6] = 8;keys[7][7] = 0;keys[7][8] = 1;keys[7][9] = 2;keys[7][10] = 5;keys[7][11] = 10;keys[7][12] = 4;keys[7][13] = 3;keys[7][14] = 9;keys[7][15] = 6;keys[8][0] = 12;keys[8][1] = 8;keys[8][2] = 1;keys[8][3] = 2;keys[8][4] = 4;keys[8][5] = 9;keys[8][6] = 3;keys[8][7] = 7;keys[8][8] = 14;keys[8][9] = 13;keys[8][10] = 10;keys[8][11] = 6;keys[8][12] = 5;keys[8][13] = 11;keys[8][14] = 0;keys[8][15] = 15;keys[9][0] = 14;keys[9][1] = 13;keys[9][2] = 11;keys[9][3] = 7;keys[9][4] = 12;keys[9][5] = 9;keys[9][6] = 3;keys[9][7] = 15;keys[9][8] = 10;keys[9][9] = 4;keys[9][10] = 8;keys[9][11] = 1;keys[9][12] = 2;keys[9][13] = 5;keys[9][14] = 6;keys[9][15] = 0;keys[10][0] = 7;keys[10][1] = 14;keys[10][2] = 15;keys[10][3] = 12;keys[10][4] = 11;keys[10][5] = 5;keys[10][6] = 10;keys[10][7] = 13;keys[10][8] = 6;keys[10][9] = 3;keys[10][10] = 9;keys[10][11] = 8;keys[10][12] = 4;keys[10][13] = 2;keys[10][14] = 0;keys[10][15] = 1;keys[11][0] = 15;keys[11][1] = 11;keys[11][2] = 12;keys[11][3] = 9;keys[11][4] = 3;keys[11][5] = 6;keys[11][6] = 7;keys[11][7] = 8;keys[11][8] = 1;keys[11][9] = 2;keys[11][10] = 4;keys[11][11] = 13;keys[11][12] = 10;keys[11][13] = 5;keys[11][14] = 14;keys[11][15] = 0;keys[12][0] = 14;keys[12][1] = 1;keys[12][2] = 3;keys[12][3] = 6;keys[12][4] = 13;keys[12][5] = 10;keys[12][6] = 5;keys[12][7] = 11;keys[12][8] = 7;keys[12][9] = 15;keys[12][10] = 12;keys[12][11] = 9;keys[12][12] = 2;keys[12][13] = 8;keys[12][14] = 4;keys[12][15] = 0;keys[13][0] = 2;keys[13][1] = 14;keys[13][2] = 12;keys[13][3] = 9;keys[13][4] = 15;keys[13][5] = 4;keys[13][6] = 5;keys[13][7] = 10;keys[13][8] = 8;keys[13][9] = 0;keys[13][10] = 1;keys[13][11] = 3;keys[13][12] = 6;keys[13][13] = 7;keys[13][14] = 13;keys[13][15] = 11;keys[14][0] = 6;keys[14][1] = 12;keys[14][2] = 8;keys[14][3] = 0;keys[14][4] = 1;keys[14][5] = 2;keys[14][6] = 4;keys[14][7] = 9;keys[14][8] = 3;keys[14][9] = 7;keys[14][10] = 14;keys[14][11] = 5;keys[14][12] = 11;keys[14][13] = 15;keys[14][14] = 13;keys[14][15] = 10;keys[15][0] = 5;keys[15][1] = 10;keys[15][2] = 4;keys[15][3] = 9;keys[15][4] = 3;keys[15][5] = 7;keys[15][6] = 15;keys[15][7] = 14;keys[15][8] = 13;keys[15][9] = 8;keys[15][10] = 0;keys[15][11] = 1;keys[15][12] = 12;keys[15][13] = 2;keys[15][14] = 11;keys[15][15] = 6;keys[16][0] = 12;keys[16][1] = 9;keys[16][2] = 3;keys[16][3] = 6;keys[16][4] = 2;keys[16][5] = 5;keys[16][6] = 10;keys[16][7] = 4;keys[16][8] = 8;keys[16][9] = 1;keys[16][10] = 7;keys[16][11] = 15;keys[16][12] = 14;keys[16][13] = 0;keys[16][14] = 11;keys[16][15] = 13;keys[17][0] = 11;keys[17][1] = 7;keys[17][2] = 15;keys[17][3] = 14;keys[17][4] = 13;keys[17][5] = 6;keys[17][6] = 12;keys[17][7] = 9;keys[17][8] = 2;keys[17][9] = 5;keys[17][10] = 10;keys[17][11] = 4;keys[17][12] = 8;keys[17][13] = 0;keys[17][14] = 1;keys[17][15] = 3;keys[18][0] = 6;keys[18][1] = 12;keys[18][2] = 8;keys[18][3] = 0;keys[18][4] = 1;keys[18][5] = 2;keys[18][6] = 4;keys[18][7] = 3;keys[18][8] = 7;keys[18][9] = 15;keys[18][10] = 14;keys[18][11] = 13;keys[18][12] = 10;keys[18][13] = 9;keys[18][14] = 5;keys[18][15] = 11;keys[19][0] = 7;keys[19][1] = 15;keys[19][2] = 14;keys[19][3] = 12;keys[19][4] = 9;keys[19][5] = 2;keys[19][6] = 4;keys[19][7] = 8;keys[19][8] = 0;keys[19][9] = 1;keys[19][10] = 5;keys[19][11] = 10;keys[19][12] = 3;keys[19][13] = 6;keys[19][14] = 11;keys[19][15] = 13;keys[20][0] = 10;keys[20][1] = 4;keys[20][2] = 9;keys[20][3] = 2;keys[20][4] = 8;keys[20][5] = 0;keys[20][6] = 1;keys[20][7] = 3;keys[20][8] = 6;keys[20][9] = 12;keys[20][10] = 7;keys[20][11] = 14;keys[20][12] = 5;keys[20][13] = 11;keys[20][14] = 13;keys[20][15] = 15;keys[21][0] = 15;keys[21][1] = 14;keys[21][2] = 12;keys[21][3] = 8;keys[21][4] = 0;keys[21][5] = 1;keys[21][6] = 2;keys[21][7] = 4;keys[21][8] = 9;keys[21][9] = 3;keys[21][10] = 7;keys[21][11] = 13;keys[21][12] = 10;keys[21][13] = 11;keys[21][14] = 6;keys[21][15] = 5;keys[22][0] = 8;keys[22][1] = 5;keys[22][2] = 11;keys[22][3] = 6;keys[22][4] = 13;keys[22][5] = 4;keys[22][6] = 9;keys[22][7] = 3;keys[22][8] = 12;keys[22][9] = 10;keys[22][10] = 1;keys[22][11] = 2;keys[22][12] = 7;keys[22][13] = 15;keys[22][14] = 14;keys[22][15] = 0;keys[23][0] = 10;keys[23][1] = 1;keys[23][2] = 8;keys[23][3] = 12;keys[23][4] = 14;keys[23][5] = 15;keys[23][6] = 7;keys[23][7] = 11;keys[23][8] = 13;keys[23][9] = 6;keys[23][10] = 3;keys[23][11] = 9;keys[23][12] = 2;keys[23][13] = 5;keys[23][14] = 4;keys[23][15] = 0;keys[24][0] = 4;keys[24][1] = 8;keys[24][2] = 1;keys[24][3] = 2;keys[24][4] = 5;keys[24][5] = 11;keys[24][6] = 7;keys[24][7] = 15;keys[24][8] = 14;keys[24][9] = 13;keys[24][10] = 10;keys[24][11] = 9;keys[24][12] = 3;keys[24][13] = 12;keys[24][14] = 0;keys[24][15] = 6;keys[25][0] = 12;keys[25][1] = 9;keys[25][2] = 3;keys[25][3] = 7;keys[25][4] = 14;keys[25][5] = 13;keys[25][6] = 10;keys[25][7] = 5;keys[25][8] = 11;keys[25][9] = 2;keys[25][10] = 4;keys[25][11] = 8;keys[25][12] = 1;keys[25][13] = 15;keys[25][14] = 0;keys[25][15] = 6;keys[26][0] = 5;keys[26][1] = 8;keys[26][2] = 0;keys[26][3] = 1;keys[26][4] = 3;keys[26][5] = 6;keys[26][6] = 13;keys[26][7] = 11;keys[26][8] = 7;keys[26][9] = 14;keys[26][10] = 2;keys[26][11] = 12;keys[26][12] = 10;keys[26][13] = 15;keys[26][14] = 4;keys[26][15] = 9;keys[27][0] = 2;keys[27][1] = 4;keys[27][2] = 8;keys[27][3] = 0;keys[27][4] = 1;keys[27][5] = 3;keys[27][6] = 7;keys[27][7] = 15;keys[27][8] = 14;keys[27][9] = 12;keys[27][10] = 5;keys[27][11] = 11;keys[27][12] = 6;keys[27][13] = 13;keys[27][14] = 9;keys[27][15] = 10;keys[28][0] = 4;keys[28][1] = 9;keys[28][2] = 3;keys[28][3] = 7;keys[28][4] = 15;keys[28][5] = 14;keys[28][6] = 12;keys[28][7] = 8;keys[28][8] = 1;keys[28][9] = 2;keys[28][10] = 5;keys[28][11] = 11;keys[28][12] = 13;keys[28][13] = 10;keys[28][14] = 6;keys[28][15] = 0;keys[29][0] = 0;keys[29][1] = 1;keys[29][2] = 3;keys[29][3] = 7;keys[29][4] = 14;keys[29][5] = 12;keys[29][6] = 9;keys[29][7] = 6;keys[29][8] = 13;keys[29][9] = 11;keys[29][10] = 8;keys[29][11] = 15;keys[29][12] = 2;keys[29][13] = 5;keys[29][14] = 10;keys[29][15] = 4;keys[30][0] = 9;keys[30][1] = 2;keys[30][2] = 4;keys[30][3] = 8;keys[30][4] = 0;keys[30][5] = 1;keys[30][6] = 5;keys[30][7] = 11;keys[30][8] = 6;keys[30][9] = 12;keys[30][10] = 3;keys[30][11] = 7;keys[30][12] = 15;keys[30][13] = 14;keys[30][14] = 13;keys[30][15] = 10;keys[31][0] = 5;keys[31][1] = 11;keys[31][2] = 7;keys[31][3] = 15;keys[31][4] = 14;keys[31][5] = 13;keys[31][6] = 10;keys[31][7] = 6;keys[31][8] = 12;keys[31][9] = 9;keys[31][10] = 2;keys[31][11] = 4;keys[31][12] = 8;keys[31][13] = 1;keys[31][14] = 3;keys[31][15] = 0;				
											
				next_s = 1;			
			end

				 
			1: begin
				lfsr1_reset = 0;				
				lfsr2_reset = 0;
				lfsr3_reset = 0;										
				
				if(counter < MAX_GEN) begin
					OneGen_nrst = 1;
					OneGen_start = 1;
					
					next_s = 4;
				end				
				else begin				
					counter = 0;
					next_s = 12;
				end
			end		

			4: begin
				next_s = 2;
			end			

			2: begin
				OneGen_start = 0;
				
				if(OneGen_done == 1) begin					
				
					keys <= mkeys;									
					
					OneGen_nrst = 0;	
					
					counter = counter + 1;
					
					next_s = 3;
				end
			end	
			
			3: begin
				next_s = 1;
			end			
			
			10:begin
				if(counter < 16) begin
					tx_byte = mkeys[counter1][counter];
					transmit = 1;
					next_s = 11;
				end
				else begin
					counter = 0;
					next_s = 16;
				end
			end
			
			11:begin
				if(!is_transmitting) begin
					transmit = 0;
					counter = counter + 1;
					next_s = 10;
				end					
			end
			
			16:begin
				if(counter1 < 32) begin
					tx_byte = "x";
					transmit = 1;					
					next_s = 17;
				end
			end			
			
			17:begin
				if(!is_transmitting) begin
					transmit = 0;					
					counter1 = counter1 + 1;
					next_s = 10;
				end								
			end
			
			12: begin
				tx_byte = SEED1;
				transmit = 1;
				counter = 0;
				next_s = 13;
			end			
			
			13:begin
				if(!is_transmitting) begin
					transmit = 0;
					tx_byte = SEED2;
					transmit = 1;
					next_s = 14;					
				end
			end
			
			14:begin
				if(!is_transmitting) begin
					transmit = 0;
					tx_byte = SEED3;
					transmit = 1;
					next_s = 15;					
				end
			end
			
			15:begin
				if(!is_transmitting) begin
					transmit = 0;
					next_s = 10;
				end
			end
		
		endcase
	end

	
endmodule
	

	

Crossover2.sv


parameter KEY_LEN = 16;	

module Crossover2(input clk, input nrst, input start, output reg cross2_done, 
	input byte alpha,
	input [3:0] k0[0:15],
	input [3:0] k1[0:15],
	output reg [3:0] c0[0:15],
	output reg [3:0] c1[0:15]
	);
		
	reg [3:0] counter2, counter4;	
	reg [4:0] counter1, counter3; 
	
	reg [2:0] current_s, next_s;
	parameter INIT = 0 , IDLE=1 ;
	
	reg flag0[0:15]; 
	reg flag1[0:15];	
	
	reg [4:0] a;
	
	initial begin
		current_s = INIT;
	end
	
	always @(posedge clk or negedge nrst) begin	
	
		if(nrst == 0)			
			current_s = IDLE;
		else begin
			current_s = next_s;			
		end	
	end	
	
	always @(posedge clk) begin			
	
		case(current_s)
		
	   /*0*/INIT: begin		
				int i;
				cross2_done = 0;
				counter1 = 0;					
				
				for(i=0; i < KEY_LEN; i=i+1) begin
					flag0[i] = 0;
					flag1[i] = 0;		
				end					
				
				next_s = 2;
			end	
				 
	   /*1*/IDLE: begin				
				cross2_done = 0;	   
				if(start == 0) begin			
					next_s = IDLE;					
				end
				else begin 				
					next_s = INIT;					
				end		
			end	
			
			2: begin
				if(counter1 < alpha) begin
				
					c0[counter1] = k0[counter1];
					flag0[k0[counter1]] = 1;
						
					c1[counter1] = k1[counter1];
					flag1[k1[counter1]] = 1;
					
					counter1 = counter1 + 1;
				end					
				else begin
					counter1 = alpha;					
					counter2 = 0;
					
					counter3 = alpha;
					counter4 = 0;
					
					next_s = 3;
				end
			end			

			3: begin
				if(counter1 < KEY_LEN) begin
					a = k1[counter2];					
					if(flag0[a] == 0) begin
						c0[counter1] = k1[counter2];
						flag0[a] = 1;
						
						counter1 = counter1 + 1;
					end
					counter2 = counter2 + 1;						
				end
				
				if(counter3 < KEY_LEN) begin
					a = k0[counter4];
					if(flag1[a] == 0) begin
						c1[counter3] = k0[counter4];
						flag1[a] = 1;
						
						counter3 = counter3 + 1;
					end
					counter4 = counter4 + 1;						
				end
				
				if(counter1	 == KEY_LEN && counter3 == KEY_LEN) begin	
					cross2_done = 1;
					next_s = IDLE;				
				end	
			end	
			
		endcase
	end

	
endmodule
	

Fitness.sv


	module Fitness(input clk, input nrst, input start, input [3:0] key[0:15], output reg f_done, output reg [19:0] f);

	parameter BLOCK_LEN = 16;	
	parameter TXT_LEN = 8192;	
	parameter BLOCK_ITERATIONS = 512;// BLOCK_LEN / TXT_LEN; // 8192/16 = 512;
	parameter SCALE = 8; // 2^16 / TXT_LEN // 65536 / 256 = 256
	parameter INIT = 0, INIT_RAM_T= 18 ,IDLE=1 , DECRYPT = 2, COUNT_T = 3, FITNESS = 4, WAIT = 5;
			
	reg [4:0] current_s, next_s;
	int counter;	
	
	// ramR = ram Refrence Text (or refTx)
	reg[12:0] rR_addr;
	reg [0:7] rR_in;
	reg rR_wren;
	wire [0:7] rR_out;	
		
	Ram8x8192	ramR(
		.address (rR_addr),
		.clock (clk),
		.data (rR_in),
		.wren (rR_wren),
		.q (rR_out)
		);	
			
	// ramD = ram DECRYPTed Text (or decTxt)
	reg[12:0] rD_addr;
	reg [0:7] rD_in;
	reg rD_wren;
	wire [0:7] rD_out;	
		
	Ram8x8192	ramD(
		.address (rD_addr),
		.clock (clk),
		.data (rD_in),
		.wren (rD_wren),
		.q (rD_out)
		);		

	// ramT = ram T[27][27] which stores count of each peer of letter in decrypted text
	reg[12:0] rT_addr;
	reg [0:7] rT_in;
	reg rT_wren;
	wire [0:7] rT_out;	
		
	Ram8x8192_init0	ramT(
		.address (rT_addr),
		.clock (clk),
		.data (rT_in),
		.wren (rT_wren),
		.q (rT_out)
		);			

	reg[9:0] rE_addr;
	reg [0:11] rE_in;
	reg rE_wren;
	wire [0:11] rE_out;	
		
	Ram12x1024 ramE(
		.address (rE_addr),
		.clock (clk),
		.data (rE_in),
		.wren (rE_wren),
		.q (rE_out)
		);			

	// init not sansthesizable:
	
	int a;	
	
	initial begin // todo : vared kardane e[27][27] be surate dasti					
		current_s = INIT;			
	end	
	
	always @(posedge clk or negedge nrst) begin	
	
		if(nrst == 0)			
			current_s = IDLE;
		else begin
			current_s = next_s;			
		end	
	end

	always @(posedge clk) begin			
			
		case(current_s)
		
	   /*0*/INIT: begin		
				rR_addr = 0;
				rR_wren = 0;					
				rD_addr = 0;												
				rD_wren = 1;								
				counter = 0;	
				f_done = 0;
				rT_addr = 0;
				rT_in = 0;					
				rT_wren = 1;
				f = 0;
				
				next_s  = INIT_RAM_T; // 1 clk montazer mandan baraye amadne avalin khaneye ramR ruye buse an;
			end
			
			INIT_RAM_T: begin
				if(rT_addr < 1024) begin																							
					rT_addr = rT_addr + 1;	
					next_s = INIT_RAM_T;	
				end
				else begin
					counter = 0;
					rT_addr = 0;
					rT_wren = 0;
					next_s = 17;
				end
			end
			
			17:begin
				next_s = DECRYPT;
			end
		
	   /*1*/IDLE: begin							
				if(start == 0) begin				
					next_s = IDLE;
				end
				else begin 				
					next_s = INIT;					
				end		
				
				f_done = 0;
				counter = 0;		
			end					

			DECRYPT: begin
								
				if(counter < TXT_LEN) begin 
					rR_addr = counter-counter%16 + key[counter%16];																	
					
					rD_addr = counter;					
													
					next_s = 19;					
				end	
				else begin					
					counter = 0;
					rD_addr = 0;
					rD_wren = 0;
					next_s = COUNT_T;
				end
			end	

			19: begin
				next_s = 20;
			end
			
			20: begin
				rD_in = rR_out;				
					
				counter = counter + 1;					
			
				next_s = DECRYPT;
			end			

			COUNT_T: begin	

				rT_wren = 0;
											
				if(counter < TXT_LEN-1) begin	
					rD_addr = counter;
					next_s = 8;
				end		
				else begin				
					counter = 0;
					next_s = FITNESS;					
				end
			end
			
			8: begin
										
				if(rD_out == " ")
					a = 26;
				else 
					a = rD_out - "a";
									
				rD_addr = counter + 1;	

				next_s = 9;
				
			end

			9: begin
				next_s = 10;				
			end
			
			10: begin
			
				int b;
					
				if(rD_out == " ")
					b = 26;
				else
					b = rD_out - "a";
					
					rT_addr = 27*a+b;

				next_s = 13;			
				
			end
			
			13: begin
				next_s = 14;
			end
			
			14: begin
			
				rT_in = rT_out + 1;// T[a][b] =  T[a][b] + 1;				
				rT_wren = 1;
				
				//T[a][b] = rT_out + 1; // !TODO: You must Comment this line because of avoiding latch in synthsizing part !!! ***
							
				counter = counter + 1;
				
				next_s = COUNT_T;
																						
			end			

			
			FITNESS: begin	
				
				if(counter < 729 ) begin	
					rT_addr = counter;
					rE_addr = counter;	
					next_s = 15;					
				end	
				else begin
					// INIT T = 0 FOR NEXT LOOP; BUT CHANGE INIT E FROM etalon.txt FROM RAM IN STATE INIT;					
					counter = 0;	
					
					f_done = 1;
					
					next_s = IDLE;	
				end	
			end
			
			15: begin
				next_s = 16;
			end
				
			
			16:begin
				int tmp;
				
				tmp = rT_out*SCALE - rE_out; // TODO: T[j][k]*2048
				
				if (tmp > 0) // baraye ghadre motlagh 
					f += tmp;
				else begin
					f -= tmp;	
					
				//T[j][k] = 0;		
				end											
						
				counter = counter + 1;

				next_s = FITNESS;	
			end		

		endcase	
	end	
	
endmodule 

Mutation32.sv


module Mutate32(input clk, input nrst, input start, output reg done,
	input reg [3:0] ckeys[0:31][0:15],
	output reg lfsr2_en,
	input byte lfsr2_out,	
	output reg lfsr3_en,
	input byte lfsr3_out,			
	output reg [3:0] mkeys[0:31][0:15]
	);// define other input & outputs here
	
	
	reg [3:0] ckey[0:15];	
	wire [3:0] mkey[0:15];
	
	Mutate1 mutate1(ckey, lfsr3_out, mkey);		
	
	reg [5:0] counter;

	reg [4:0] current_s, next_s;		
	parameter INIT = 0 , IDLE=1 ; // define other state parameters here or just write number of states in switch case without any parameter
	
	initial begin
		current_s = INIT;
	end
	
	always @(posedge clk or negedge nrst) begin	
	
		if(nrst == 0)			
			current_s = IDLE;
		else begin
			current_s = next_s;			
		end	
	end	
	
	always @(posedge clk) begin			
	
		case(current_s)
		
	   /*0*/INIT: begin		
				// write initialize functions here									
				counter = 0;
				done = 0;
				
				next_s = 2;
			end	
				 
	   /*1*/IDLE: begin		
				done = 0;
				if(start == 0) begin			
					next_s = IDLE;					
				end
				else begin 				
					next_s = INIT;					
				end		
			end	
			
			2: begin
				if(counter < 32) begin															
					lfsr2_en = 1;
					next_s = 3;				
				end				
				else begin
					done = 1;
					next_s = IDLE;
				end				
					
			end	
			
			
			3: begin					
				lfsr2_en = 0;
				if(lfsr2_out < 8'd64) begin
					lfsr3_en = 1;
					ckey = ckeys[counter];
					next_s = 4;
				end 
				else begin		
					mkeys[counter] = ckeys[counter];
					counter = counter + 1;
					next_s = 2;
				end
			end	
			
			4:begin
				lfsr3_en = 0;
				mkeys[counter] = mkey;
				counter = counter + 1;
				next_s = 2;				
			end
			
		endcase
	end

	
endmodule
	

		

sort.sv


module sort(input clk, input nrst, input start, input done);

	reg sort_rst;
	reg [31:0]f_load;
	reg sort_start;	
	reg sort_done;		
	reg [4:0]sorted_index[0:31];
	
	reg [20:0] f32[0:31];			
	
	assign f32[0] = 1728704;
	assign f32[1] = 1560449;
	assign f32[2] = 1699330;
	assign f32[3] = 1405955;
	assign f32[4] = 1558532;	
	
	bublesort #(21,32)	
	sort1 (
		.clk(clk), 
		.rst(sort_rst), 
		.load_i(f_load), 
		.f32(f32),
		.index(sorted_index),
		.start_i(sort_start), 		
		.sort_done(sort_done)		
	);

	reg [3:0] current_s, next_s;
	parameter INIT = 0,  IDLE=1 ;
	
	initial begin
		current_s = INIT;
	end	
	
	always @(posedge clk or negedge nrst) begin	
	
		if(nrst == 0)			
			current_s = IDLE;
		else begin
			current_s = next_s;			
		end	
	end	
	
	always @(posedge clk) begin			
	
		case(current_s)
		
	   /*0*/INIT: begin		
				int i;		
				sort_rst = 1;				
				next_s = 3;
			end					  
	
	   /*1*/IDLE: begin							
				if(start == 0) begin			
					next_s = IDLE;
				end
				else begin 				
					next_s = INIT;					
				end		
			end	
			
			3:begin				
				sort_rst = 0;
				next_s = 4;
			end						
			
			4: begin							
				int i;
				for(i=0; i<32; i=i+1) 
					f_load[i] = 1;									
				next_s = 5;																
			end				

			5: begin
				int i;
				for(i=0; i<32; i=i+1) 
					f_load[i] = 0;
					
				sort_start = 1;	
				
				next_s = 6;	
			end						
			
			6:begin
				sort_start = 0;
			end
			
		endcase
	end
			
endmodule	
	

bitsplit.sv


module bitsplit(
    input   clk,
    input   bit1_i,
    input   bit2_i,
    output  largebit_o,
    output  smallbit_o,
    input   swap_i,
    output  swap_o,
    input   run_i,
    output  run_o
    );

    reg     r_bit1;
    reg     r_bit2;
    reg     r_small_bit;
    reg     r_large_bit;
    reg     r_compare_result;
    reg     r_freeze_compare;
    reg [0:1]   r_swap;
    reg [0:1]   r_run;

    wire    w_different_bits;

    always @(posedge clk)
        begin
            if (~run_i) begin
                r_freeze_compare <= 0;      end
            else if (w_different_bits) begin
                r_freeze_compare <= 1;      end
        end
        
    always @(posedge clk)
        begin
            if (~run_i) begin
                r_compare_result <= 0;      end
            else if (~r_freeze_compare) begin
                if (bit1_i & ~bit2_i)   begin
                    r_compare_result <= 1;  end
                else begin
                    r_compare_result <= 0;  end                
                end
        end

    always @(posedge clk)
        begin
            r_bit1 <= bit1_i;
            r_bit2 <= bit2_i;
            if (~r_compare_result) begin
                r_small_bit <= r_bit1;
                r_large_bit <= r_bit2;   end
            else begin
                r_small_bit <= r_bit2;
                r_large_bit <= r_bit1;   end
        end
        
    always @(posedge clk)
        begin
            r_swap[0] <= swap_i;
            r_swap[1] <= r_swap[0] | r_compare_result;
        end

    always @(posedge clk)
        begin
            r_run[0] <= run_i;
            r_run[1] <= r_run[0];
        end
        
    assign w_different_bits = bit1_i ^ bit2_i;

    assign largebit_o = r_large_bit;
    assign smallbit_o = r_small_bit;
    assign swap_o = r_swap[1];
    assign run_o = r_run[1];
    
endmodule

	

intgenerator.sv


module intgenerator #(parameter N_BITS=8, parameter K_NUMBERS=8)
    (
    input   clk,
    input   rst,
    input   run_i,
    input   swap_i,
    output  done_o,
    output  interrupt_o
    );

    parameter P_PULSES = (2*(K_NUMBERS+11))/(N_BITS+4);
    parameter P_WIDTH = $clog2(P_PULSES)+1;
    
    reg     r_run_delay;
    reg     r_swap_delay;
    reg [P_WIDTH:0]   r_pulses;
    reg     r_done;
    
	wire w_falling_run;
	
    always @(posedge clk)
        begin
            if (rst) begin
                r_run_delay <= 1'b0;
                r_swap_delay <= 1'b0;    end
            else begin
                r_run_delay <= run_i;
                r_swap_delay <= swap_i;  end            
        end
        
    always @(posedge clk) 
        begin
            if (rst || (r_pulses[P_WIDTH])) begin
                r_pulses <= P_PULSES - 1;            end
            else if (w_falling_run) begin
                if (~r_swap_delay) begin
                    r_pulses <= r_pulses - 1;        end
                else begin
                    r_pulses <= P_PULSES - 1;        end
                end
        end
    
    always @(posedge clk) 
        begin
            /*if (rst) begin
                r_done <= 1'b0;                      end
            else*/ if (w_falling_run & (~r_swap_delay)) begin
                r_done <= 1'b1;                      end
            else begin
                r_done <= 1'b0;                      end
        end
    
    assign w_falling_run = (~run_i) & r_run_delay;

    assign done_o = r_done;
    assign interrupt_o = r_pulses[P_WIDTH];
        
endmodule
	

stageen.sv


module stageen #(parameter N_BITS=8)
(
    input   clk,
    input   load,
    input  [N_BITS-1:0] data_i,
    output [N_BITS-1:0] data_o,
    input   swap_i,
    output  swap_o,
    input   run_i,
    input   run_late_i,
    output  run_o,
    input   bit_i,
    output  bit_o,
    input   value_i,
    output  value_o
    );

    reg[N_BITS-1:0]    r_data;
    
    wire    w_large_bit;
    wire    w_small_bit;
    wire    w_swap_o;
    wire    w_run_o;
    
    always @(posedge clk)
        begin
            if (load) begin
                r_data <= data_i;                        end
            else if (run_i | run_late_i) begin
                r_data <= {r_data[N_BITS-2:0],value_i};  end
        end
        
    bitsplit split_module (
        .clk(clk),
        .bit1_i(bit_i),
        .bit2_i(r_data[N_BITS-1]),
        .largebit_o(w_large_bit),
        .smallbit_o(w_small_bit),
        .swap_i(swap_i),
        .swap_o(w_swap_o),
        .run_i(run_i),
        .run_o(w_run_o)
        );
    
    assign data_o = r_data;
    assign swap_o = w_swap_o;
    assign run_o = w_run_o;
    assign bit_o = w_large_bit;
    assign value_o = w_small_bit;
    
endmodule
	

uart.sv


	
module uart(
    input clk, // The master clock for this module
    input rst, // Synchronous reset.
    input rx, // Incoming serial line
    output tx, // Outgoing serial line
    input transmit, // Signal to transmit
    input [7:0] tx_byte, // Byte to transmit
    output received, // Indicated that a byte has been received.
    output [7:0] rx_byte, // Byte received
    output is_receiving, // Low when receive line is idle.
    output is_transmitting, // Low when transmit line is idle.
    output recv_error // Indicates error in receiving packet.
    );

parameter CLOCK_DIVIDE = 1302; // clock rate (50Mhz) / (baud rate (9600) * 4)

// States for the receiving state machine.
// These are just constants, not parameters to override.
parameter RX_IDLE = 0;
parameter RX_CHECK_START = 1;
parameter RX_READ_BITS = 2;
parameter RX_CHECK_STOP = 3;
parameter RX_DELAY_RESTART = 4;
parameter RX_ERROR = 5;
parameter RX_RECEIVED = 6;

// States for the transmitting state machine.
// Constants - do not override.
parameter TX_IDLE = 0;
parameter TX_SENDING = 1;
parameter TX_DELAY_RESTART = 2;

reg [10:0] rx_clk_divider = CLOCK_DIVIDE;
reg [10:0] tx_clk_divider = CLOCK_DIVIDE;

reg [2:0] recv_state = RX_IDLE;
reg [5:0] rx_countdown;
reg [3:0] rx_bits_remaining;
reg [7:0] rx_data;

reg tx_out = 1'b1;
reg [1:0] tx_state = TX_IDLE;
reg [5:0] tx_countdown;
reg [3:0] tx_bits_remaining;
reg [7:0] tx_data;

assign received = recv_state == RX_RECEIVED;
assign recv_error = recv_state == RX_ERROR;
assign is_receiving = recv_state != RX_IDLE;
assign rx_byte = rx_data;

assign tx = tx_out;
assign is_transmitting = tx_state != TX_IDLE;

always @(posedge clk) begin
	if (rst) begin
		recv_state = RX_IDLE;
		tx_state = TX_IDLE;
	end
	
	// The clk_divider counter counts down from
	// the CLOCK_DIVIDE constant. Whenever it
	// reaches 0, 1/16 of the bit period has elapsed.
   // Countdown timers for the receiving and transmitting
	// state machines are decremented.
	rx_clk_divider = rx_clk_divider - 1;
	if (!rx_clk_divider) begin
		rx_clk_divider = CLOCK_DIVIDE;
		rx_countdown = rx_countdown - 1;
	end
	tx_clk_divider = tx_clk_divider - 1;
	if (!tx_clk_divider) begin
		tx_clk_divider = CLOCK_DIVIDE;
		tx_countdown = tx_countdown - 1;
	end
	
	// Receive state machine
	case (recv_state)
		RX_IDLE: begin
			// A low pulse on the receive line indicates the
			// start of data.
			if (!rx) begin
				// Wait half the period - should resume in the
				// middle of this first pulse.
				rx_clk_divider = CLOCK_DIVIDE;
				rx_countdown = 2;
				recv_state = RX_CHECK_START;
			end
		end
		RX_CHECK_START: begin
			if (!rx_countdown) begin
				// Check the pulse is still there
				if (!rx) begin
					// Pulse still there - good
					// Wait the bit period to resume half-way
					// through the first bit.
					rx_countdown = 4;
					rx_bits_remaining = 8;
					recv_state = RX_READ_BITS;
				end else begin
					// Pulse lasted less than half the period -
					// not a valid transmission.
					recv_state = RX_ERROR;
				end
			end
		end
		RX_READ_BITS: begin
			if (!rx_countdown) begin
				// Should be half-way through a bit pulse here.
				// Read this bit in, wait for the next if we
				// have more to get.
				rx_data = {rx, rx_data[7:1]};
				rx_countdown = 4;
				rx_bits_remaining = rx_bits_remaining - 1;
				recv_state = rx_bits_remaining ? RX_READ_BITS : RX_CHECK_STOP;
			end
		end
		RX_CHECK_STOP: begin
			if (!rx_countdown) begin
				// Should resume half-way through the stop bit
				// This should be high - if not, reject the
				// transmission and signal an error.
				recv_state = rx ? RX_RECEIVED : RX_ERROR;
			end
		end
		RX_DELAY_RESTART: begin
			// Waits a set number of cycles before accepting
			// another transmission.
			recv_state = rx_countdown ? RX_DELAY_RESTART : RX_IDLE;
		end
		RX_ERROR: begin
			// There was an error receiving.
			// Raises the recv_error flag for one clock
			// cycle while in this state and then waits
			// 2 bit periods before accepting another
			// transmission.
			rx_countdown = 8;
			recv_state = RX_DELAY_RESTART;
		end
		RX_RECEIVED: begin
			// Successfully received a byte.
			// Raises the received flag for one clock
			// cycle while in this state.
			recv_state = RX_IDLE;
		end
	endcase
	
	// Transmit state machine
	case (tx_state)
		TX_IDLE: begin
			if (transmit) begin
				// If the transmit flag is raised in the idle
				// state, start transmitting the current content
				// of the tx_byte input.
				tx_data = tx_byte;
				// Send the initial, low pulse of 1 bit period
				// to signal the start, followed by the data
				tx_clk_divider = CLOCK_DIVIDE;
				tx_countdown = 4;
				tx_out = 0;
				tx_bits_remaining = 8;
				tx_state = TX_SENDING;
			end
		end
		TX_SENDING: begin
			if (!tx_countdown) begin
				if (tx_bits_remaining) begin
					tx_bits_remaining = tx_bits_remaining - 1;
					tx_out = tx_data[0];
					tx_data = {1'b0, tx_data[7:1]};
					tx_countdown = 4;
					tx_state = TX_SENDING;
				end else begin
					// Set delay to send out 2 stop bits.
					tx_out = 1;
					tx_countdown = 8;
					tx_state = TX_DELAY_RESTART;
				end
			end
		end
		TX_DELAY_RESTART: begin
			// Wait until tx_countdown reaches the end before
			// we send another transmission. This covers the
			// "stop bit" delay.
			tx_state = tx_countdown ? TX_DELAY_RESTART : TX_IDLE;
		end
	endcase
end

endmodule

LFSR.sv


	

// lfsr with polynomial: X^8 + X^6 + X^5 + X^4 + 1 module LFSR (input clk, input reset , input enable , input byte SEED, output byte out); wire linear_feedback; assign linear_feedback = (out[7] ^ out[5] ^ out[4] ^ out[3]); always @(posedge clk) begin if (reset) begin // active high reset // out <= {SEED[6],SEED[5], // SEED[4],SEED[3], // SEED[2],SEED[1], // SEED[0], (SEED[7] ^ SEED[5] ^ SEED[4] ^ SEED[3])}; out <= SEED; end else if (enable == 1) begin out <= {out[6],out[5], out[4],out[3], out[2],out[1], out[0], linear_feedback}; end end endmodule // End Of Module counter