Ruisheng's Photo

Ruisheng Wang Ruisheng's name

PhD Student

SMART Interconnects Group
Department of Electrical Engineering
3740, McClintok Ave., EEB 224
University of Southern California
Los Angeles, CA 90089-2562

Email: ruishenw AT usc DOT edu

Resume


My name is "Ruisheng Wang". I was born in Taiyuan, Shanxi, China.

Currently I am a fourth year Ph.D student in Department of Electrical Engineering, in Viterbi School of Engineering, at University of Southern California, working with Professor Timothy Mark Pinkston in the area of Computer Architecture


Research Interests


Current Interests: Cache Capacity and Memory Bandwidth Management in Chip Multiprocessors, Interconnection Network Design
Previous Interests: High Performance Router Design(Switch Architecture and Packet Scheduler)

Education



Publications


Journal Papers

1. Lizhong Chen, Ruisheng Wang and Timothy Mark Pinkston, "Efficient Implementation of Globally-aware Network Flow Control". in Journal of Parallel and Distributed Computing (JPDC), volume 72, issue 11, November 2012. (pdf)

Conference Papers

1. Ruisheng Wang, Lizhong Chen and Timothy Mark Pinkston, "Bubble Coloring: Avoiding Routing- and Protocol-induced Deadlocks With Minimal Virtual Channel Requirement". In Proceedings of the 27th International Conference on Supercomputing (ICS), June 2013.(pdf)
2. Ruisheng Wang, Lizhong Chen and Timothy Mark Pinkston, "An Analytical Performance Model for Partitioning Off-Chip Memory Bandwidth". to appear in IEEE International Parallel & Distributed Processing Symposium (IPDPS), May 2013. (pdf)
3. Lizhong Chen, Ruisheng Wang and Timothy Mark Pinkston, "Critical Bubble Scheme: An Efficient Implementation of Globally-aware Network Flow Control". In Proceedings of the 25th IEEE International Parallel & Distributed Processing Symposium (IPDPS 2011). (pdf)
4. Yuho Jin, Ruisheng Wang, Woojin Choi and Timothy Mark Pinkston, "Thread Criticality Support in On-Chip Networks". In Proceedings of Third International Workshop on Network on Chip Architectures (NoCArc 2010), held in conjunction with the 43rd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-43). (pdf)
5. Ruisheng Wang, Youjian Zhao, Hongtao Guan and Guanghui Yang, "HOBRP: A Hardware Optimized Packet Scheduler that Provides Tunable End-to-end Delay Bound". In Proceedings of 17th IEEE International Workshop on Quality of Service (IWQoS 2009). (pdf)
6. Ruisheng Wang, Youjian Zhao and Ting Zhou, "Achieving 100% Throughput in a Two-stage Multicast Switch". In Proceedings of 23rd International Conference on Information Networking (ICOIN 2009). (pdf)

Experiences


Smart Interconnects Group at University of Southern California, USA
Ericsson, San Jose, USA Computer Network and Protocol Testing Laboratory at Tsinghua University, Beijing, China
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The University of Southern California does not screen or control the content on this website and thus does not guarantee the accuracy, integrity, or quality of such content. All content on this website is provided by and is the sole responsibility of the person from which such content originated, and such content does not necessarily reflect the opinions of the University administration or the Board of Trustees