R Naseer, J Draper, Parallel Double Error Correcting Code Design to Mitigate Multi-Bit Upsets in SRAMs, in review at: 34th European Solid-State Circuits Conference (ESSCIRC) 2008

R Naseer, Y Boulghassoul, M Bajura, J Sondeen, S Stansberry, J Draper,  Single-Event Effects Characterization and Soft Error Mitigation in 90nm Commercial-Density SRAMs, submitted to: IASTED CAS 2008

M A Bajura, Y Boulghassoul, R Naseer, S DasGupta, A Witulski, J Sondeen, S Stansberry, J Draper, L Massengill, and J Damoulakis, Models and algorithmic limits for an ECC-based approach to hardening sub-100nm SRAMs, IEEE Transactions on Nuclear Science, Aug 2007

R Naseer, J Draper, Y Boulghassoul, S DasGupta, A Witulski, Critical charge and SET pulse widths for combinational logic in commercial 90nm technology, 17th GLSVLSI, March 2007

R Naseer, Y Boulghassoul, J Draper, S DasGupta, A Witulski, Critical charge characterization for soft error rate modeling in 90nm SRAM, ISCAS, May 28-30, 2007

R Naseer, R Z Bhatti, J Draper, Analysis of Soft Error Mitigation Techniques for Register Files in IBM Cu-08 90nm Technology, 49th IEEE MWSCAS, August 2006

R Naseer, J Draper, DF-DICE: A Scalable Solution for Soft Error Tolerant Circuit Design, IEEE ISCAS, May 2006

R Naseer, J Draper, The DF-DICE Storage Element for Immunity to Soft Errors, 48th IEEE MWSCAS, August 2005

  Information Sciences Institute

Publications

I have a number of publications on mitigating radiation-induced transient effects on VLSI circuits in ultra-deep sub-micron technologies.