Personal Information

Gender

Male

Email

najibiko@usc.edu

Date of Birth

Aug 18, 1977

Nationality

Iran

Marital Status

Married

Education

2010-present

PhD Student in Computer Engineering, Department of Electrical Engineering, University of Southern California, Los Angeles, USA. Major: Computer Architecture-Asynchronous Circuit Design & Synthesis.

2001-2003

Masters in Computer Engineering, Computer Engineering and Information Technology Department, Amirkabir University of Technology, Tehran, Iran. Major: Computer Architecture-Asynchronous Circuits.

1996-2001

B.S. in Electrical Engineering, Computer and Electrical Engineering Department, Shahid-Beheshti University, Tehran, Iran. Major: Electronics.

Research Interests

CAD for emerging technology challenges,  Multi-core Architectures,

Performance Driven Synthesis, High Performance-Low Power Design, Asynchronous Circuits, Statistical Timing Analysis, Highly Concurrent Systems.

Awards and Honors

2004

The First Ranked student among the admited student in 2001-2002 in Computer Engineering (Masters Degree)  by gaining GPA of 18.24 (out of 20)

2001

First class with distinct (Ranked 1^st) student in Electrical Engineering (B.S.)

Academic Experience

2010-spring

2009-2010

Teaching Assistant, System Level & Board level Microprocessor Design, Viterbi School of Engineering, USC

Visiting Researcher, Asynchronous Lab, California Institute of Technology

2001-Present

Research on Asynchronous Synthesis and Circuit Design.

Fall 2007

Teaching Instructor.  Fundamentals of Digital Electronics, Amirkabir University of Technology.

Spring 2007

Teaching Instructor.  VLSI Digital Design, Amirkabir University of Technology.

Fall-Spring

2006-2007

Teaching Instructor.  VLSI Digital Design, Qazvin AZAD University.

Teaching Instructor.  Digital Design, Qazvin AZAD University.

Teaching Instructor.  VHDL, Qazvin AZAD University.

Fall  2002

Teaching Assistantship.  Electronic Lab.

Work Experience

2003-2006

Design & Implementation of Persia

A Fully Automatic Asynchronous Synthesis Tool

(presented at demo and exhibition  session of async08)

I served as a Project Manager, System Designer, and Code Developer

Amirkabir University – Asynchronous Lab

2001-2002

Implementation & Optimization of AUT Core

(A general RISC processor used in an industrial VOIP Implementation)

Design and Implementation of AHB Bus, and Functional Units of the Core for ASIC. I also contributed in improving the overall performance of the Core on FPGA by applying minor architectural modifications and utilizing Implementation Constraints.

Amirkabir University – AUT Core Design Group

2002

Design and Implementation of a Simple Power Router

(Part of ATLAS Layout Tool)

I mainly contribute to initiate the infra-structure of the power router.

Amirkabir University – VLSI & CAD Lab

Technical Skills

OS

User experience of UNIX and Microsoft Windows systems

HDL Modeling

General: Verilog, SystemVerilog, SystemC, VHDL. Asynchronous Circuits:  CSP, CAST, Verilog-CSP, Balsa, Petri-Nets, STG.

CAD Tools

Synopsis: Design Compiler, PrimeTime, PrimePower – Cadence: Silicon Ensemble,  VerilogXL – Others:  Leonardo,  Xilinx Foundation, Quartus, ModelSim, Balsa, Petrify, MAGIC, Spice.

Programming Languages

Professional expertise in C/C++ programming & MATLAB.

Perl, Tcl, and Python.

Hardware Design

Synchronous & Asynchronous Circuit Design, Lowpower Design Techniques, Architectural Design, Performance/Power Optimization

EDA Tool Development

Experienced in CAD Algorithms for VLSI, Hardware Synthesis Algorithms for Synchronous & Asynchronous circuits.

FPGAs

Expert in Xilinx & Altera FPGAs, Advance knowledge of Mapping, Floorplaning, Placement, Routing Constraints

Testing Hardware

Familiar with Functional Verification Methodology, Design for Testability, Scan, BIST

Publications

2008

Sharareh ZamanZadeh, Mehrdad Najibi, Hossein Pedram, et. al. “Reimbursing the Handshake Overhead of Asynchronous Circuits using Compiler Pre-Synthesis Optimizations”. EuroMicro08, 2008, Italy.

Mehrdad Najibi, Hossein Pedram: “Compensating Algorithmic-Loop Performance Degradation in Asynchronous Circuits Using Hardware Multi-threading”. ISVLSI 2008: 507-510 (poster)

2007

Mehrdad Najibi, Mahtab Niknahad, Hossein Pedram. “Performance Evaluation of Asynchronous Circuits Using Abstract Probabilistic Timed Petri Nets”, ISVLSI07, 2007, Brazil.

Mehrdad Najibi, Kamran Saleh, and Hossein Pedram. Using Standard ASIC Back-End for QDI Asynchronous Circuits: Dealing with Isochronic Fork Constraint, GLSVLSI/07, March 11-13, 2007, Stresa-Lago Maggiore, Italy.

Atabak Mahram, Mehrdad Najibi, Hossein Pedram: An asynchronous fpga logic cell implementation. ACM Great Lakes Symposium on VLSI 2007: 176-179. (poster)

Mahtab Niknahad, Behnam Ghavami, Mehrdad Najibi and Hossein Pedram "A new method for Behavioral Power Estimation of Asynchronous Circuits", 13th Iranian Computer Conference, Iran, Feb2007.

Mahtab Niknahad, Kamran Saleh, Mehrdad Najibi and Hossein Pedram "CRO- A Conditional Restructuring Method for High-Level Optimization of Asynchronous Systems ", 13th Iranian Computer Conference, Iran, Feb2007.

2006

Esmail Amini, Mehrdad Najibi, Hossein Pedram: Globally Asynchronous Locally Synchronous Wrapper Circuit based on Clock Gating. ISVLSI 2006: 193-199.

Mehrdad Najibi, Mostafa Salehi, Ali Afzali-Kusha, Massoud Pedram, S. Mehdi Fakhraie, Hossein Pedram, Dynamic Voltage and Frequency Management Utilizing a Variable Update Interval Scheme, ICCAD 2006.

E. Amini, M. Najibi, H. Pedram, Automatic Generation of Pausible Clock Based GALS Warpper Circuits, Proceedings of the 11th International CSI computer Conference, Jan 2006.

Publications (cont.)

2005

S. Moein Hosseini, M. Najibi, K. Saleh, H. Pedram, Evaluating the Partitioning of GALS Systems Using Abstract System Level Modeling Proceedings of the 11th International CSI computer Conference, Jan 2006.

E. Amini, M. Najibi, H. Pedram, Globally Asynchronous Locally Synchronous Wrapper Circuits based on Clock Gating, Proceedings of the IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures (ISVLSI), March 2006.

M. Mirzaaghatabar, M. Najibi, K. Saleh, H. Pedram, Exploring the Design of A RISC Asynchronous Processor Using Persia Asynchronous Toolset Proceedings of the 14th Iranian Conference on Electrical Engineering (ICEE2006), May 2006.

M. Salehi, M. Najibi, H. Pedram, A. Afzali Koosha, S.M. Fakhraie, Implementing a Dynamic Voltage and Frequency Control System to Reduce Power Consumption of a Processor, (Persian),  Proceedings of the 14th Iranian Conference on Electrical Engineering (ICEE2006), May 2006.

Mehrdad Najibi, Mohsen Naderi, Hossein Pedram, Mehdi Sedighi, Module-based Synthesis of Behavioral Verilog Descriptions to Asynchronous Circuits, Proceedings of the 13th Iranian Conference on Electrical Engineering (ICEE2005), May 2005.

K. Saleh, M. Najibi, M. Naderi, H. Pedram, M. Sedighi, A Novel Clock Generation Scheme for Globally Asynchronous Locally Synchronous Systems: An FPGA-Validated Approach, Proceedings of the 15th GLSVLSI ,Chicago, April 2005.

M. Najibi, K. Saleh, M. Naderi, H. Pedram, M. Sedighi, Prototyping Globally Asynchronous Locally Synchronous Circuits on Commercial Synchronous FPGAs, Proceedings of the 16th IEEE International Workshop on Rapid System Prototyping RSP2005, June 2005.

M. H. Shafiaabadi, M. Najibi, H. Pedram, M. Naderi, K. Saleh, New Methods to Reduce Energy and Area in Asynchronous Circuits Following the Decomposition Stage, Proceedings of the 10th Annual Computer Society of Iran Computer Conference (CSICC2005), Feb 2005.

References

DBLP, IEEE, ACM Portal

Further references are available upon request.