10982 Roebling Ave
Los Angeles, CA 90024
PhD. Candidate, Electrical Engineering, University of Southern California, Los Angeles, CA.
Expected graduation date: Summer 2013. GPA: 3.9
Dissertation: Optimization of Conditional Asynchronous Circuits with Average-Case Performance Constraints
Advisor: Professor Peter Beerel
Masters of Science, Electrical Engineering, University of Southern California, Los Angeles, CA.
Emphasis: Synchronous/Asynchronous Circuit Design. 2011
Masters of Science, Computer Engineering, Amirkabir University of Technology, Tehran, Iran. 2003
Bachelor of Science, Electrical Engineering, National University of Iran, Tehran, Iran. 2001
o Relevant Courses:
á Computer Aided Design I (Physical Design)
á Computer Aided Design II (Logic Synthesis)
á Advance Computer System Architecture
á Advanced VLSI System Design
á Asynchronous Circuit Design
á Low Power Circuit Design
á Analysis of Algorithms
o Research Interests:
á VLSI CAD algorithms development.
á Low power circuit design.
á Circuit Synthesis and Optimization.
á Globally Asynchronous Locally Synchronous (GALS) systems.
á FPGA Prototyping.
Programming/Scripting: C/C++, Perl, Tcl, Shell scripts.
HDL/Modeling: SystemVerilog, SystemC, RTL Verilog, VHDL, MATLAB.
CAD Tools: Cadence Encounter, Virtuoso, Simvision, RTL Compiler. Synopsis Design Compiler, PrimeTime, HSpice. Mentor ModelSim. Asynchronous: Proteus, Petrify.
Digital Design: synchronous & asynchronous circuit design, low power design, performance/power optimization, layout design, FPGA prototyping.
EDA Tool Development: CAD algorithms for VLSI circuits, synthesis algorithms for synchronous & asynchronous circuits.
Project Management/Source Control: wiki, svn, doxigen, bugzilla.
Platforms: expert user of Linux/Unix based system.
o CondSlacker: Slack-matching of Conditional Asynchronous Circuits (Ph.D. Thesis, USC, 2012)
á Developed a theoretical upper bound on average-case performance of conditional asynchronous circuits and formulated the bound as a linear program.
á Implemented the conditional slack-matching as an LP using GNU GLPK linear program solver (C++, GLPK, STL Lib, GDB).
á The results show up to 20% area saving for a conditional asynchronous circuits benchmark based on ISCAS89 circuits (Proteus Flow, RC Synthesis, Asynchronous Optimizations, P&R).
o DDR2 Memory Controller Design and Timing Closure (Fall 2011, USC, EE577b)
á Designed and verified the controller using RTL Verilog (Cadence Simvision).
á Synthesized (Synopsis Design Compiler) and verified the design post-synthesis.
á Generated layout (Cadence Encounter) and optimized the circuit to meet timing post layout (PrimeTime).
o SVC2RTL: SystemVerilog front-end for Async Synthesis Flow (Summer 2011, USC)
á Developed and implemented a tool to convert SystemVerilogCSP to synthesizable RTL Verilog (C++, Perl, TCL, Cadence RC).
o SVparser: A General Parser for IEEE1800-2009 SystemVerilog (Summer 2011, USC)
á Developed a GLR parser to generate abstract syntax tree for SystemVerilog (GNU flex/bison).
á Designed C++ iterators to traverse the abstract syntax tree in code order and code structure order.
á Managed a graduate student to implement the parser
o Hierarchical ClockGating in SIS (Fall10, EE681, USC)
á Developed a greedy algorithm to reduce power consumption in clock tree by inserting clock gating cells hierarchically into the clock tree based on the activity factor of the flops.
á Clustered flops to be clock-gated together such that the static activity factor of the clusters, calculated using BDDs, remains optimally low (C, SIS Logic synthesis).
o Custom Layout Design of a 32-bit Array Multiplier (Spring10, EE577a, USC)
á Designed and verified replicateable library cells for the multiplier (Virtuoso, Spice, Specter).
á Replicated and manually placed cells to implement the multiplier and verified the functionality post layout (Spice).
o A Partitioning, Placement & Routing Tool for Multi-FPGA Systems (Spring10, EE680, USC)
á Partitioned a specific multi-FPGA architecture with a fixed inter-FPGA interconnect between available FPGAs, placing logic cells & pins, and routing the signals to meet given timing requirements.
á Responsible for the implementation of global & detailed routing, and also was involved in the design of the algorithms for partitioning and placement (C++, STL Lib).
o Persia-A Fully Automatic Asynchronous Synthesis Tool (2006-2009, AUT & Caltech Async Labs)
á Persia is a tool set to design asynchronous circuits staring from Verilog. The synthesis process involves data driven decomposition of the data flow, followed by logic, and template synthesis (C++).
á Responsible for the implementation of data driven decomposition, technology mapping, and also contributed in architecting the design flow.
á Modified the template synthesis algorithms to improve timing and area of the circuit.
á Persia was selected for industrial and academic tool demonstration in Async 2008 (Newcastle, UK, 2008).
Teaching Assistant: System & Board Level Microprocessor Design, Asynchronous VLSI Design. Viterbi School of Engineering, USC (Spring 2010 – Fall 2012)
Research Assistance: Asynchronous CAD-VLSI Group, USC (Fall 2011 - present)
Visiting Researcher: Asynchronous Lab, California Institute of Technology (2009-2010)
á The AUT-Core is a RISC Processor with ARM-ISA designed for VoIP Application.
á Responsible for designing and implementing AMBA AHB bus controller using RTL Verilog, and later for improving the performance of the core on Excalibur ARM EPXA10 FPGA boards through retiming the design and constraining logic mapping, placement and routing. For the ASIC version I was responsible for designing the high performance ALU blocks at logic level (FPGA P&R Constraints, Verilog RTL, Architectural design).
Qualcomm Innovation Fellowship (QInF) Finalist, 2012.
Best TA award, USC 2013.
Top student in my master program, among 20 students.
Top student in my bachelor program, among 70 students.
1) Najibi, M.; Beerel, P.A.; "Deriving Performance Bounds for Conditional Asynchronous Circuits using Linear Programing," Asynchronous Circuits and Systems (ASYNC), 2013 19th IEEE International Symposium on, Santa Monica, USA, 19-23 May 2013.
2) Najibi, M.; Beerel, P.A.; "Performance Bounds of Asynchronous Circuits with Mode-Based Conditional Behavior," Asynchronous Circuits and Systems (ASYNC), 2012 18th IEEE International Symposium on, pp.9-16, Denmark, 7-9 May 2012.
3) Salehi, M.E.; Samadi, M.; Najibi, M.; Afzali-Kusha, A.; Pedram, M.; Fakhraie, S.M.; "Dynamic Voltage and Frequency Scheduling for Embedded Processors Considering Power/Performance Tradeoffs," Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol.19, no.10, pp.1931-1935, Oct. 2011.
4) Ghavami, B.; Pedram, H.; Najibi, M.; "An EDA tool for implementation of low power and secure crypto-chips", Computers & Electrical Engineering, Volume 35, Issue 2, March 2009, pp. 244-257.
5) Zamanzadeh, S.; Mirza-Aghatabar, M.; Najibi, M.; Pedram, H.; Sadeghi, A.; "Reimbursing the Handshake Overhead of Asynchronous Circuits using Compiler Pre-Synthesis Optimizations," Digital System Design Architectures, Methods and Tools, 11th EUROMICRO Conference on, pp.290-297, Italy, 3-5 Sept. 2008,
6) Najibi, M.;,Saleh, K.; Pedram, H; "Using Standard ASIC back-end for QDI Asynchronous Circuits: dealing with isochronic fork constraint". In Proceedings of the 17th ACM Great Lakes symposium on VLSI, Italy, 2007.
7) Amini, E.; Najibi, M.; Jeddi, Z.; Pedram, H.; "FPGA Implementation of Gated Clock based Globally Asynchronous Locally Synchronous Wrapper Circuits," Signals, Circuits and Systems, International Symposium on, Romania, pp.1-4, July 2007.
8) Mahram, A.; Najibi, M.; Pedram, H.; "An Asynchronous FPGA Logic Cell Implementation". In Proceedings of the 17th ACM Great Lakes symposium on VLSI. ACM, New York, NY, USA, 2007.
9) Najibi, M.; Niknahad, M.; Pedram, H.; ÒPerformance Evaluation of Asynchronous Circuits Using Abstract Probabilistic Timed Petri NetsÓ, ISVLSI07, 2007, Brazil.
10) Amini, E.; Najibi, M.; Pedram, H.; "Globally Asynchronous Locally Synchronous Wrapper Circuit based on Clock Gating," Proceedings of the IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures, Karlsruhe, Germany, March 2006.
11) Najibi, M.; Salehi, M; Afzali-Kusha, A.; Pedram, M.; Fakhraie, M.; "Dynamic Voltage and Frequency Management Utilizing a Variable Update Interval Scheme", ICCAD, San Jose, 2006.
12) Najibi, M.; Saleh, K.; Naderi, M.; Pedram, H.; Sedighi, M.; "Prototyping Globally Asynchronous Locally Synchronous Circuits on Commercial Synchronous FPGAs", Proceedings of the 16th IEEE International Workshop on Rapid System Prototyping, Montreal, Canada, June 2005.