Damon Moazen

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    Education

 

                            M.Sc. Degree in Computer Engineering                                                                         Aug 2009

                            Concentration: VLSI/Digital Design

                            University of Southern California, Los Angeles, CA

                    

                            B.Sc. Degree in Electrical and Computer Engineering,                                                May 2007                             Concentration: Digital Design

                            California State University, Northridge (CSUN), CA

 

    Honors                    

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Deans list Fall 05, Spring 06, Spring 07

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College of Engineering and Computer Honors List Fall 2005, Spring 2006,

     Fall 06, and Spring 07

 

 

    Industry Experience                   

 

                            Summer Intern                                                                                                                         2009

                            Boston Scientific Corporation – Neuromodulation R&D, Valencia, CA

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Design/Development of a test board to integrate a Bluetooth module to

the remote controller (RC) and the Charger utilizing and programming

a Texas Instrument (TI) microcontroller

 

                                 Summer Intern                                                                                                                        2008

                            Boston Scientific Corporation – Neuromodulation R&D, Valencia, CA

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Developing a feasibility test plan to test and verification

of the latest version of the Falcon III remote controller

 

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Develop, synthesis and simulation of a behavioral Verilog module for the

Boundary-Scan Chain Test for the Implantable Pulse Generator (IPG)

 

    Teaching Experience                

 

                            Teaching Assistant

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EE477L: “MOS VLSI Circuit design”, to Prof. S. Nazarian

University of southern California,                                                                             2008 - 2009

                                         

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EE101 “Introduction to Digital Logic Circuit Design”, to Prof.M.Redekopp

University of southern California,                                                                             2007 - 2008

 

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Tutoring for Electrical Engineering courses, Math and Physics at the School

Of Engineering at (CSUN),                                                                                      2005 - 2007

 

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Student assistant in the Faculty/staff Computer Lab

Santa Monica College,                                                                                            2003 - 2004

 

    Graduate Level Courses  

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Computer Aided Design of Digital Systems I (EE 680)

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VLSI System Design A (EE 577A)

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VLSI System Design B (EE 577B)

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Asynchronous VLSI Design (EE 552) 

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Computer Systems Architecture (EE557)

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Non-Linear Integrated Analog Circuit Design (EE479)

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Computer system organization (EE 457X)

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MOS VLSI Circuit Design (EE 477)

    Bachelor Level Courses

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Verilog-HDL Design 

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VHDL–Logic Design              

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FPGA/ASICS Design 

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Digital Systems Design

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Design of Digital Computer                

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Fundamental Control System

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Electromagnetic Fields and Waves 

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Probabilistic Systems

    Graduate level Projects   

          

                            FPGA Compiler:

                            Implementation of the min-cut placement algorithm in C for an FPGA compiler

                           

                            Troy Wide Word Processor:

                            Behavioral Verilog HDL design, implementation, simulation, synthesis and Static timing

                            analysis for pre and post synthesis net list of the Troy Wide Word Processor, utilizing

                            NC-sim, Design Compiler, PrimTime, and NanoSim respectively

                               

                            Viterbi Decoder:

                            Behavioral Verilog HDL Implementation, simulation, synthesis and Static timing

                            analysis for pre and post synthesis net list of a Viterbi Decoder,using

                            NC-sim, Design Compiler, PrimTime, and NanoSim respectively 

 

                            DDR2 Controller:

                            Behavioral Verilog HDL Implementation, simulation, synthesis and Static timing analysis

                            for pre and post synthesis net list of the DDR2 Controller, using NC-sim, Design Compiler,

                            PrimTime, and NanoSim respectively 

 

                            Direct Digital Synthesizer:

                            Design/Implementation/Layout and Simulation of a Direct Digital Synthesizer (DDS),

                            involving a 1Kbit SRAM, 16bit Accumulator, 32bit Decoder, and a DAC, utilizing CADANCE

                            tools in 180nm technology and NanoSim

                           

                            Asynchronous Network on chip:

                            Frontend design of a Asynchronous Network on chip (NoC), using Verilog CSP,

                            and Behavioral Verilog modeling

                   

                            Neuron-network:

                            Design/ layout/ implementation and simulation of a Neuron-network, utilizing

                            CADNCE tools

 

    Senior Design Projects                       

                            

                             Individual Project

                             Design and implementation of a Floating-point Frequency Counter (TTL) Utilizing Cascaded

                             CMOS BCD Counters and Monostable Multivibrator ICs.

                                  

                             Group Project

Design/implementation of a Dual Input Port Digital Spectrum Analyzer,

with the maximum 1MHz real-time bandwidth, consisting of an Analog to Digital converter, LM555CN clock generator and two Elexol I/O USB 24 DIP communication modules, Utilizing Labview for the Software part of the design

 

    Computer Skills                    

                            Programming languages: C, Assembly, MATLAB, Verilog, Verilog CSP

                            Synopsys: HSPICE, NanoSim, Design Compiler, PrimeTime

                            Cadence: Composer Schematic, Virtuoso Layout Editor, Encounter, NC-Sim   

                            Platforms: UNIX, Windows 

         Software: PSpice, Winspice, Altera (QuartusII), Xilinx ISE, Labview, ModelSim, OrCAD,

         Microsoft Office       

                                                             

    References                   

                            Massoud Pedram                                                                    (213) 740-4458

                            Professor, Dept. of Electrical Eng.-systems, University Of Southern California,

                            Los Angeles, California                                                  

 

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