Mohammad Mirza-Aghatabar

I got my PhD from Electrical Engineering Department at University of Southern California (USC) under supervision of Prof. Melvin A. Breuer & Prof. Sandeep K. Gupta.

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EDUCATION

bullet PhD. Computer Engineering (CENG)

Electrical Engineering Department at University of Southern California, Los Angeles, CA, Aug. 2008 – May. 2012.

Dissertation Title:Redundancy Driven Design of Logic Circuits for Yield/Area Maximization in Emerging Technologies

Advisor: Melvin A. Breuer & Prof. Sandeep K. Gupta

Major GPA: 4.00

bullet M.S. Electrical Engineering

               Electrical Engineering Department at University of Southern California, Los Angeles, CA, Aug. 2008 – Dec. 2011.

GPA: 4.00

bullet M.S. Computer Architecture

Computer Engineering, Sharif University of Technology, Tehran, IRAN, Sep. 2005 – Jan. 2008.

Dissertation Title: “Evaluation of Traffic Pattern Effect on Power Density in Torus-based NoC”,

Advisor: Prof. Shaahin Hessabi

GPA: 19.04 / 20.00 (Second Student between 30 students)

bullet B.S. Computer Engineering, Major: Hardware Engineering & Software Engineering

Computer Engineering & IT, AmirKabir University of Technology, Tehran, IRAN, Sept. 2001 – Sept. 2005

Dissertation Title: “Design and Simulation of an asynchronous 8-bit V8-uRISC microprocessor”,

Advisor: Prof. Hossein Pedram

                GPA: 18.45 / 20.00 (Top student between more than 60 students)

HONORS AND REWARDS

bullet Best Paper Diploma, for the best Regular Paper on EWDTS’07 Symposium, the outstanding contribution in Design and Test
bullet I got the citation of the top student in B.S among 60 students.
bullet I got the citation of the agreement in physic & mathematic Olympiad in country

 

RESEARCH INTERESTS

bullet Design for Yield and Manufacturability
bullet Test issues of VLSI Circuits
bullet Network-On-Chip Design
bullet Asynchronous Circuit Design

 

OUR DEVELOPED TOOLS

     Please click here for more info

 

JOURNAL PAPERS

[1] M. Mirza-Aghatabar, A. Sadeghi, ”An Asynchronous, Low Power and Secure Framework for Network-On-Chips", in International Journal of Computer Science and Network Security, Vol. 8  No. 7  pp. 214-223, 2008.

 

CONFERENCE PAPERS (in reverse chronological order)

[18] M. Mirza-Aghatabar, M. A. Breuer, S. K. Gupta, "A design flow to maximize yield/area of physical devices via redundancy", to be appeared in Proceedings of the International Test Conference (ITC), November 2012.

[17] M. Mirza-Aghatabar, M. A. Breuer, S. K. Gupta, S. Nazarian, "Theory of Redundancy for Logic Circuits to Maximize Yield/Area ", in Proceedings of the International Symposium on Quality Electronic Design (ISQED), pp. 663-671, March 2012.

[16] M. Mirza-Aghatabar, M. A. Breuer, S. K. Gupta, "Yield/area maximization of logic circuits: From theorem to implementation", IEEE Int’l. Workshop on Defect and Adaptive Test Analysis (DATA-2011), Anaheim CA, Sept. 22-23, 2011.

[15] M. Mirza-Aghatabar, M. A. Breuer, S. K. Gupta, "Theory of logical partitioning for yield/area maximization using redundancy, IEEE Int’l Workshop on Design for Manufacturing and Yield (DFM&Y 2011), San Diego, CA, June 6, 2011.

[14] M. Mirza-Aghatabar, M. A. Breuer, S. K. Gupta, " HYPER: a Heuristic for Yield/area imProvEment using Redundancy in SoC ", in Proceedings of the 19th IEEE Asian Test Symposium (ATS), pp. 249-254, Dec 2010.

 

[13] M. Mirza-Aghatabar, M. A. Breuer, S. K. Gupta, "Algorithms to maximize yield and enhance yield/area of pipeline circuitry by insertion of switches and redundant modules", in Proceedings of the 13th IEEE Design, Automation and Test in Europe (DATE), pp. 1249-1254, March 2010.

 

[12] M. Mirza-Aghatabar, M. A. Breuer, S. K. Gupta, "SIRUP: Switch Insertion in RedUndant Pipeline Structures for Yield and Yield/Area Improvement", to appear in Proceedings of the 18th IEEE Asian Test Symposium (ATS), 23-26 November 2009.

 

[11] H. Kooti, M. Mirza-Aghatabar, A. Tavakkol, S. Hessabi, ”Energy analysis of re-injection based deadlock recovery routing algorithms”, in Proceedings of 10th IEEE International Symposium on System-on-Chip (SoC), 4-6 November 2008.

 

[10] S. Zamanzadeh, M. Mirza-Aghatabar, M. Najibi, H. Pedram, A. Sadeghi, ”Reimbursing the handshake overhead of asynchronous circuits using compiler pre-synthesis optimizations", to appear in Proceedings of the 11th IEEE Euromicro Conference on Digital System Design (DSD), 3-5 September 2008.

 

[9] A. Rasooli, M. Mirza-Aghatabar, S. Khorsandi, "Introduction of Novel Dispatching Rules for Grid Scheduling Algorithms," in Proceedings of International Conference on Computer and Communication Engineering (ICCCE08), pp. 1072-1078,  13-15 May, 2008.

 

[8] A. Rasooli, M. Mirza-Aghatabar, S. Khorsandi, "Introduction of Novel Rule Based Algorithms for Scheduling in Grid Computing Systems," in Proceedings of the IEEE Second Asia International Conference on Modeling and Simulation, pp. 138-143,  13-15 May, 2008.

 

[7] M. Mirza-Aghatabar, A. Tavakkol, H. Sarbazi Azad, "An adaptive software-based deadlock recovery technique," 22nd International Conference on Advanced Information Networking and Applications (AINA), pp. 514-519, 25-28 March, 2008.

 

[6] M. Mirza-Aghatabar, S. koohi, S. Hessabi, D. Rahmati, "An Adaptive Approach to Manage the Number of Virtual Channels," 22nd International Conference on Advanced Information Networking and Applications (AINA), pp. 353-358, 25-28 March, 2008.

 

[5] S. Koohi, M. Mirza-Aghatabar, S. Hessabi, and Massoud Pedram, " High Level Power and Throughput Models for Mesh-based Network-on-Chips Evaluating Effects of Traffic Models,"  in Proceedings of 21th International Conference on VLSI Design, pp. 415-420, 4-8 January 2008.

[4] S.Koohi, M. Mirza-Aghatabar, S. Hessabi, "Evaluation of Traffic Pattern Effect on Power Consumption in Mesh and Torus Network-on-Chips," in Proceedings  of the IEEE International Symposium on Integrated Circuits(ISIC), pp. 512-515, 26-28 Sept. 2007.

 

[3] M. Mirza-Aghatabar, A. Rasooli, B. Ghavami, Sh. Hessabi, “A new Approach to support Fault Simulation of Delay Insensitive Asynchronous Circuits with Synchronous Toolset,” in Proceedings of the 5th IEEE East-West Design & Test Symposium (EWDTS’07), pp. 243-248, 7-10 Sept. 2007. (Best Paper Diploma)

[2] M. Mirza-Aghatabar, B. Jafarpour, H. Ajerlou, S. G. Miremadi, H. Pedram, “FTARM: Fault Tolerant Asynchronous RISC Microprocessor Using Watchdog Module,” in Proceedings of the 5th IEEE East-West Design & Test Symposium (EWDTS’07), pp. 217-223, 7-10 Sept. 2007.

 

[1] M. Mirza-Aghatabar, S. Koohi, S. Hessabi, and Massoud Pedram, "An empirical investigation of Mesh and Torus NoC topologies under different routing algorithms and traffic models," in Proceedings  of the 10th IEEE Euromicro Conference on Digital System Design (DSD) , pp. 19-26, Luebeck-Germany, 29-31 August, 2007.

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