PROJECTS:
1) CISCO SYSTEMS, CALIFORNIA – Testing of Linksys Routers, Multimedia Network Storage Devices, Wireless A/V Home Entertainment devices, Intelligent Backup tools: Developing test plans; firmware testing; functionality and eco-system testing; testing for synchronization, interoperability, CPU and Network Utilization, etc, automating the test cases. TITLE: Engineering Intern May 2009 - Present
2) CSRE, INDIAN INSTITUTE OF TECHNOLOGY-BOMBAY – Chandrayaan-1 lunar probe: Performed Data Processing of Polarimetric Synthetic Aperture Radar (PolSAR) for Target Identification and Classification. The PolSAR was used in the SAR Interferometry and Remote Sensing project of the Chandrayaan-1 Lunar probe. TITLE: Project Intern Jul 2006 - Jul 2007
3) VLSI DESIGN & RESEARCH CENTER – Designed and developed a kernel debugger that monitors the context switches, task state switches, and inter-task communication events & displays these activities on a Windows host. Kernel - MicroC/OS-II on ARM7 target board. TITLE: Kernel Programming Intern Dec 2007 - Mar 2008
4) AIR INDIA LIMITED – Designed and Developed test equipments for various equipments (Temperature Indicator, Triple Pressure Indicator and Universal Logic Communication Card) in Boeing 747-400 Aircraft. TITLE: Systems Engineer – Intern Dec 2003 - May2004
5) LARSEN & TOUBRO LTD – Worked on PLC programming using ladder logic and scheme drawing in Eplan and AutoCAD TITLE: Automation Project Intern Jun 2002 - Dec 2002
RESEARCH:
1). INFORMATION SCIENCES INSTITUTE (ISI), UNIV OF SOUTHERN CALIFORNIA Working on Visualization for Critically Sensitive Co-ordination of Multiagent systems with Prof. Rajiv Maheswaran
2). COMPUTER SCIENCE DEPT, UNIV OF SOUTHERN CALIFORNIA Writing an Operating System for Coldfire 52259 microcontroller board with Prof Michael Crowley and Prof Mark Redekopp.
CLASS PROJECTS:
1) COMPILER DESIGN: Stage 1: Built a Scanner and Parser for translating C BNF grammar to Simple SUIF code. Divided this (SUIF IL) code into blocks (nodes) at control flow branches and mapped it into a graph to perform control flow analysis. Stage2: Performed loop optimizations, register coalescing, data flow analysis (Live Variable analysis) and performed register allocation using heuristic methods that are used to solve the NP complete graph coloring problem
2) OPERATING SYSTEMS: Implemented Locks and Condition Variables (for Synchronization), System Calls, Multi-Threading, Caching and Virtual Memory, Networking (Distributed OS) for Nachos OS Simulator in C++ (UNIX based).
3) DELAY TOLERANT NETWORK (DTN): Implemented DTN where thousands of nodes in 127 autonomously configured regions (connected by gateways), communicate with each other by routing packets using a Distance Vector protocol. Protocol tolerates packet losses, routes/nodes coming and going, large RTT and DVP issues - routing loops and count to infinity problem.
4) QUEUING SYSTEMS: Simulated M/M/1, M/M/1/B, M/M/n/B & M/G/1 queuing sys & compared their performance
5) PATH PLANNING FOR COMPUTER GAMES: Implemented A* and Theta* planning algorithms for Computer Games
6). PARALLEL COMPUTATION OF PI to study Task Decomposition and Scalability Analysis on Massively Parallel Machines
7) MOLECULAR DYNAMICS SIMULATION: Simulated Linked-list cell MD algorithm to compute Megaflop rating of a computer