Implemented the 'Tomasulo Algorithm' based out-of-order execution processor with RTL coded in VHDL

Synthesized on Xilinx Spartan-3E FPGA board

With support for speculative fetching for Branch prediction, jump instruction, load/store instructions

Copy-Free checkpoint mechanism

VHDL RTL to FPGA design flow

Designed and implemented the design on Xilinx Spartan-3E FPGA board

Efficient early branch technique with 2-bit flag was used and designed using VHDL for optimum performance

Successfully implemented a divider with Cache and CAM

Coded using VHDL and synthesized on Xilinx Spartan-3E FPGA board

Designed using VHDL an asynchronous FIFO interface

Designed with zero, one and two intermediate buffer registers and compared the performance

Width-expansion and Depth-expansion techniques

Designed and implemented Gated Clocking with and without latching circuitry

The enhancement in the performance with the different types of Gated Clocking is analysed and compared with normal clocking

Designed and impelemented a non-linear pipeline

Latency analysis; Reservation table; Minimum Achievable Latency (MAL); Initial Collision Vector (ICV)

Analysed the working of Wave pipelining and its performance over regular pipeline

Analyzed and verified the working of Time borrowing and Stealing in a Latch-based pipeline

'Retinal Neural Network' Circuit equivalents design (CMOS)

Continuing my research under Professor Dr. Alice Parker (started Fall 2010)

Research is a part of her Biomimetic Real-Time Cortex project

Designed and implemented a network of neurons representing a Line detection network

Designed the Schematics, Layout, DRC, LVS match, netlist extraction and simulation of the netlist

Analysis fo the designed network for performance and speed of working

Achieved an area/delay ratio of 6500 (approx) when maximum allowed was 10,000

Latch-based, Flip-flop-based and Domino pipeline

Designed the basic cell library and the adder cell for high performance using Logical Effort and several architectural exploirations

Oceanview script for running numerous simulations to verify the performance of the design

The designed opamp is a part of high-speed data-converter circuits used in imaging sensor products

Gain = 100dB; Phase margin = 65degrees; UGBW = 1GHz

Analysed, while designing, the performance of Telescopic and Folded cascode configurations

Filters

Broadband amplifiers

Circuits with inductive and capacitive input/output impedance

Complex Feedback Networks analysis using Signal Flow Method

Logical Effort for circuits and its effect in the design/performance