I am a graduate student in Ming Hsieh Department of Electrical Engineering at the University of Southern California pursing Master of Science in Electrical Engineering
I share a deep understanding of pipelined architectures, out of order processors, caches, cache coherency and virtual memory through my coursework in Computer System Architecture and Organization along with strong VLSI and Digital Circuit Design concepts and techniques.
I am currently looking for an Internship/Co-op and entry-level full-time in the field of Computer/Electrical Engineering focusing on Digital System Design, ASIC/VLSI/RTL Design,Verification/testing,Computer Architecture and Embedded systems starting May 2015 wherein I can contribute to the company's growth with my analytical abilities and technical skills while gaining hands-on experience.
Hardware description languague : VERILOG, VHDL
Programming languague : C, C++, PERL, Python
My Resume - Download Link
Website maintained by : Heril Chheda