Email: firstname.lastname@example.org (M): 213-590-7247 karna0490 http://in.linkedin.com/in/karnagajab 2825 Ellendale Place, Unit 5, Los Angeles, CA, US 90007 Resume: Updated Resume - Karna Gajab Education: Masters of Science, Electrical Engineering, University of Southern California, Los Angeles, CA. 2014-2016 Emphasis: Digital VLSI & CAD Expected Graduation term: Spring 2016 Bachelor of Engineering, Electronics & Communication, Gujarat Technological University, India 2008-2012 Relevant Courses: * Computer Aided Design of Digital Systems I (EE680) * VLSI System Design I (EE577A) * VLSI System Design II (EE577B)** * Diagnosis and Design of Reliable Digital Systems (EE658)** * Solid State Processing and Integrated Circuits Laboratory (EE504)** * Computer System Organization (EE457) * MOS VLSI Circuit Design (EE477L) * Directed Research (EE590) - Prof. Young Cho * Directed Research (EE590) - Prof. Mike Zyda Technical Skills Programming/Scripting: C, C++, Perl, Python, Tcl/Tk, Delphi, Shell scripts, Autohotkey HDL/CAD scripting: RTL Verilog, Cadence SKILL, SystemC EDA Tool Development: CAD Algorithms for VLSI: floorplanning, placement & routing (Backend CAD flow) CAD Tools: Cadence Virtuoso, Schematic Designer, Altium Designer, HSpice, OrCAD PSpice, Intusoft IsSpice, Model Sim, Agilent SystemVue/ADS Professional Experience EDA/Software Applications Intern -Texas Instruments Inc., Santa Clara, USA Jun 2015 - Aug 2015 * Software intern with the WEBENCH® Systems Development group at Texas Instruments, Santa Clara, USA. Directed Researcher Information Sciences Institute, OASys Lab: OASys Lab, Information Sciences Institute - Research Profile Jan 2015 - May 2015 * Design and test of a self-sustaining wireless sensor mote using MSP430F5438A control. Schematic and PCB layout were created using Altium Designer 14 and MSP programming was done in IAR Embedded Workbench. Graduate Student Researcher -GamePipe Laboratories, USC Sep 2014 - Dec 2014 * Developed a waveform plotting and matching utility code in Python to benchmark PSpice and LTSpice as target simulators for an end design. Design Engineer, Sankalp Semiconductor Pvt. Ltd, India Oct 2012 - Jun 2014 * Development ofsimulation export project dealing with SPICE model porting of anypower devicefrom the client’s designer toolinto target simulator(s). The exported SPICE model designpossesses simulation capabilitywith converging and accurate results. * Responsible for benchmarking client’s internal SPICE simulatorwith version updates. * Responsible for automating process flows in the projects using Perl, Delphi(OO-Pascal), Tcl and Autohotkey. * IBIS-AMI modelling for high speed SERDES using Agilent SystemVue® and validation using Agilent ADS®. * SPICE macro modeling for power management IC’s. Understanding the device architecture, reducing simulation time and achieving converging and accurate results.Porting PSPICE macro models to target simulators with simulation parameter analysis. Understanding the SPICE simulation algorithmic differences with different simulators to ensure converging designs with accurate results and reduced simulation time. Awards & Recognitions WEBENCH® Department Award-Texas Instruments * Received a department award from Texas Instruments' WEBENCH® team for successful execution of the simulation export project under the WEBENCH® connector’s program. Publications A functional analysis of SPICE simulations and parameters, International Journal of Science and Engineering Investigations, Vol. 2, Issue 18, July 2013, ISSN: 2251-8843 Academic Projects A placement and routing tool for a custom FPGA design Implemented a FPGA placement and routing tool for a custom FPGA configuration in C++ using STL.Simulated Annealing algorithm was utilized for anefficient and optimized placement with the objective function being minimization of the total net-length. Implemented Lee's Maze routing algorithm for routing single and multi-nets across the CLB's and pins of the FPGA. Design of a general purpose microprocessor using software and hardware componentsin 180nm tech node Implemented a general purpose 5-stage pipelined processor with decoding logic, register file, ALU, memory unit and other supporting circuity that supports13 different instruction types.Instruction fetching & decoding, Backend result verification was implemented with front-end and back-end scripts in Perl. Pipeline stalling was also handled using Perl.A512 KB SRAM design was utilized in the memory portion of the CPU.The design aimed at Area, Power and Delay minimization. FinFet design & simulation Simulated FinFet models in HSpice for optimizing SG-mode operation by finding the ideal number of fins for the design.Carried out simulations to compare the performance & power consumption of IG, LP, SG and IG/LP FinFet gate designs. Verilog RTL implementation for a 5-stage pipelined CPU Implementing a 5-stage MIPS 32-bit pipelined processor using Verilog RTL with hazard detection, forwarding and branch handling.