module Adder5bit (OutC, InA, InB, nAdd_Sub);
    output [4:0] OutC;
    input [4:0] InA;
    input [4:0] InB;
    input nAdd_Sub;

reg [4:0] OutC;

parameter ALUDelay=15;

always @(InA or InB or nAdd_Sub)
begin
        #ALUDelay
        case (nAdd_Sub)
                1'b0: //Add operation
                        OutC=InA+InB;
                1'b1: //Subtract operation
                        OutC=InA-InB;
                endcase
end

endmodule

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