// Verilog stimulus file.
// Please do not create a module in this file.

// Default verilog stimulus.

initial
begin

A[4:0] = 5'b00000;

B[4:0] = 5'b00000;

   Clk = 1'b0;
   Reset = 1'b0;
   nAdd_Sub = 1'b0;

#200
Reset=1'b1;
#200
Reset=1'b0;

#200
A[4:0] = 5'b11011;

B[4:0] = 5'b10010;

#200

A[4:0] = 5'b11001;

B[4:0] = 5'b10101;

#200

A[4:0] = 5'b11111;

B[4:0] = 5'b10001;

end

always
begin
#100 Clk=~Clk;
end

initial
begin
        $shm_open("signals.shm");
        $shm_probe("AS");
        #2000
        $shm_close();
        $finish;
end

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