Symbol Editing and Verilog Association

Created by: Recep Ozdag


  1. Change your directory to cds.

  2. %cd cds
     
  3. Run Cadence.

  4. %icfb&
     
  5. Create a new library called "sp2000_Cell".

  6. File-> New -> Library...
     
  7. Open a new Cellview in library "sp2000_Cell".

  8. File-> New ->  Cellview...

    Type "Adder5bit" for  "Cell Name" and "symbol" for "View Name"

    Draw this symbol. Then "Check and Save". Make sure you have no errors by checking the Cadence main window which is called "CIW".
    Design-> Check and Save
     

  9. Now we will associate a verilog code with the symbol. From "Design", select "Create Cellview" and "From Cellview...".

  10. Design-> Create Cellview -> From Cellview

    A new window will appear. Change "To View Name schematic" to "To View Name functional". Click OK. A new window will appear which looks like this. Edit the verilog code and make the additions so that at the end you get this code.  Save the file and quit the editor. Look at the CIW (Cadence main window) to make sure you have no errors. Another way to check that you have no errors is the write the verilog code of the symbol in another editor and save it. Then compile that code in an xterm. If you have no errors then you should not have any in Cadence either.
     

  11. Also create these following symbols and associate the verilog code given below.

  12. A 2 input AND gate. Here is the symbol. Here is the verilog code. Save it as AND2.
    A 1 bit register. Here is the symbol. Here is the verilog code. Save it as REGISTER1bit
     
  13. Now create a new Cellview in library "sp2000_Cell"

  14. File-> New -> Cellview

    Type "Tutorial8" for "Cell Name" and "schematic" for "View name"
     

  15. Instantiate the blocks we have just created  by pressing  "i". A new window will appear. Clock on "Browse". Again a new window will appear. Select the blocks we have created and drag them to your sheet. Place the blocks as in this figure. Wire the blocks by clicking on the wire icon on the left of the sheet. You can also select a thick wire for buses. Place the labels such as "B<4>" by first clicking on the wire. You will see that the wire becomes white. Then press "l". A new window will appear and write the label name in the blank box. Then click on the wire again. Include the pins. (You should already know how to do this if you have done tutorial 1). After you complete the circuit as in the previous figure, check and save. Make sure you have no errors.

  16.  
  17. Up to this step, you already know how to run the simulation by using simWaves in tutorial 3 and 4. We recommend you to use simWave in integration control.

  18.  

     
     
     
     

    The steps below show you how to use simWaves in command line mode.
     

  19. From "Tools" select "Simulation" and "Verilog_XL". A new window will appear. You may change the "Run" Directory" name, but stick with the default name for this tutorial. Click OK.

  20.  

     

    A new window called "Verilog-XL Integration Control" will appear. From "Setup" select "Netlist". In the window that appears click on "more". The window will expand. For "Netlist These Views" type "verilog functional behavioral schematic symbol", and for "Stop Netlisting at View" type "verilog functional behavioral symbol". Select "Generate Pin Map". Then click on OK. From "Stimulus" select "Verilog". Click on "Yes" on the window that appears. Select "Edit" and click on "testfixture.verilog" on the "Stimulus Options" window. The "File Name" box will automatically write the same file name. Click on OK. A new editor will appear. Type this code. Save the file and quit the editor. Close the "Stimulus Options" and "Verilog-XL Integration Control" windows.
     

  21. Open a new xterm and change your directory to ~/cds/Tutorial8.run1. Make a new directory called" waves". Copy testfixture.template and testfixture.verilog to the "waves" directory. Change to "waves" directory.

  22.  
  23. Edit the "testfixture template" file and add the these lines before the "module test;" line. Verilog must compile the verilog code of the symbols that are used in the design, then the netlist generated by Cadence which corresponds to the schematic we have entered and finally the testbench. The lines we have introduced will refer to these codes in the desired order.

  24.  
  25. Compile the verilog code by exeuting the following command

  26. %verilog testfixture.template.
     
  27. Run simWaves, select all the signals in the "test" subscope, which is in the window that appear when the "Browser/Display Tool..." is selected. Zoom in the waveforms and you should see something like this.