Created by: Sunan Tugsinavisut
Email: pgolani@usc.edu

1. We will use the design in "Symbol Editing and Verilog Assiciation (Tutorial 8)" in this tutorial.

1. Create the testbench module.
• Copy your testbench in tutorial8 to testbench.v in your directory ~/cds/sp2000_Cell.
• Modify testbench.v like this (Fig1). Notice that we just insert the interface to the old testbench.
• Compile it by verilog
• $ verilog testbench.v
• Make sure you have no errors.
2. Use "Automatic symbol generation from verilog" method to create symbol for the testbench module as follows.
• Import the design by invoke File->import->Verilog.... Fill in the option like (Fig2).
• You will get the symbol testbench in library sp2000_cell like (Fig3).
3. Create symbol for "Tutorial8" schematic (your DUT) by using "Automatic symbol generation from schematic" method.
• Open "Tutorial8" schematic
• Invoke Design->Create Cellview->From Cellview and fill in the menu (Fig4).
• You will get symbol for "Tutorial8" (Fig5).
4. Create your top level schematic between DUT and testbench.
• Open new schematic by invoke File->New->Cellview name "sp2000_top" in "sp2000_Cell" library like (Fig6).
• Connect you DUT(Tutorial8) and testbench together (Fig7) (Don't forget to add output pins).
• Make sure you have no error by "Check and Save" the design.
5. Now, you are ready to run the simulator (simWaves).
• You don't need any external testbench because you already integrate it in your design.
• Open Simulator by invoke Toos->Simulator->Verilog-XL, choose run directory Fig8.
• Change Netlist Options by invoke Setup->Netlist. (Fig9)
• set "Netlist These Views" to verilog functional behavioral schematic symbol.
• set "Stop Netlisting at Views to verilog functional behavioral symbol.
• To see all signals in hierachy (invoke Setup->Record signals).
• set "save" to All Signals (the default is Top Level Primary I/O).
• Invoke Start->Interactive. (Fig10)
• Invoke Simulation->Continue.
• Debug->Utilities->View Waveform... (Fig11).
• The result in Fig11 is the same as in Tutorial 8.