Debugging System Design using simWaves

Created by: Sunan Tugsinavisut
Email: tugsinav@usc.edu



    This tutorial will introduce you how to integrate your DUT (Design Under Test) with your testbench and then running it under integration control tool.
  1. We will use the design in "Symbol Editing and Verilog Assiciation (Tutorial 8)" in this tutorial.
  1. Create the testbench module.
  2. Use "Automatic symbol generation from verilog" method to create symbol for the testbench module as follows.
  3. Create symbol for "Tutorial8" schematic (your DUT) by using "Automatic symbol generation from schematic" method.
  4. Create your top level schematic between DUT and testbench.
  5. Now, you are ready to run the simulator (simWaves).