Automatic Symbol Generation from Verilog and Schematic
by Sangyun Kim
Automatic Symbol Generation from Verilog
Invoke any text editor you prefered and write verilog description. Save
In this tutorial we use emacs as default text editor. And this is an example
of 5bit adder verilog code.
Change your directory to cds.
Create a new library called "Tutorial".
File-> New -> Library...
From icds windows, import verilog file and make symbol and functional
description for that code.
File-> import -> verilog...
Now you can see a window named verilog
Fill in Target Library Name, Reference Libraries, Verilog Files
Reference Libraries should include Target Library. Verilog Files To
Import should contains path also.
Now Log file window pop up automatically like
Finally we can see function and symbol description under Library Tutorial.
This is automatically
generated symbol of adder5 .
Automatic Symbol Generation from Schematic
Automatic Symbol generation from schematic is easy to do. Draw a schematic.
For this tutorial we can use one bit full adder schematic like this.
The detail information of this schematic is in the Cadence Tutorial 1 and
From Composer window, we can generate symbol automatically.
Design -> Create Cellview -> From Cellview
You can see Cellview
From Cellview window. Make sure your library name, cell name, From
View Name and To View Name.
Automatic Symbol generation from schematic is done. We can see
symbol view for full adder.