Automatic Symbol Generation from Verilog and Schematic

by Sangyun Kim



Automatic Symbol Generation from Verilog
  1. Invoke any text editor you prefered and write verilog description. Save as auto.v. In this tutorial we use emacs as default text editor. And this is an example of 5bit adder verilog code.

  2.  
  3. Change your directory to cds.

  4. %cd cds
     
  5. Run Cadence.

  6. %icfb&
     
  7. Create a new library called "Tutorial".

  8. File-> New -> Library...
     
  9. From icds windows, import verilog file and make symbol and functional description for that code.

  10. File-> import -> verilog...
     
  11. Now you can see a window named verilog in.

  12. Fill in Target Library Name, Reference Libraries, Verilog Files To Import.
    Reference Libraries should include Target Library. Verilog Files To Import should contains path also.
    Click OK.
     
  13. Now Log file window pop up automatically like this.

  14.  
  15. Finally we can see function and symbol description under Library Tutorial.

  16. This is automatically generated symbol of adder5 .


Automatic Symbol Generation from Schematic
  1. Automatic Symbol generation from schematic is easy to do. Draw a schematic. For this tutorial we can use one bit full adder schematic like this. The detail information of this schematic is in the Cadence Tutorial 1 and 2

  2. .
     
  3. From Composer window, we can generate symbol automatically.

  4. Design -> Create Cellview -> From Cellview

    You can see Cellview From Cellview window. Make sure your library name, cell name, From View Name and To View Name.
    Click OK.
     

  5. Automatic Symbol generation from schematic is done. We can see this symbol view for full adder.