Verilog Frequently Asked Questions

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Q: Is there a function in verilog to generate random numbers?

Yes. It is $random(seed). The seed is optional. The random number sequence for a given seed (or no seed) will always be the same. Where b > 0, the expression ($random % b) gives a number in the following range: [(-b+1):(b-1)].

Q: I want to have a 2-bit random variable. How can I do that?

$random function call returns a 32-bit random number each time it is called. The random number is a signed integer; it can be positive or negative. Therefore, if 2-bit random varialbe is desired, you need a modulo operation as follows.

reg [1:0] R;
R = $random % 2;

Above example will generate random value between -1 to 1. If only positive is needed, use concatenation operator as follows.

reg [1:0] R;
R = {$random} % 2;

Q: What is a command to stop in verilog?

$stop and $finish. $stop system task puts the simulator into a halt mode, issues an interactive command prompt, and passes control to user. $finish system task simply causes the simulator to exit and pass control back to the host OS. Both tasks takes an optional expression parameter that determine what type of diagnostic message is printed before the interactive command prompt is issued. If no parameter is supplied, then the task defaults to a parameter value of 1.

0 : prints nothing
1 : prints simulation time and location
2 : prints simulation time, location, and statistics about the memory and CPU time used in simulation

Q: Is the following code fragment correct?

wire[2:0] LP;
initial begin
assign LP=3'b101;
end

Wrong. Any variable that is continuously assigned (using assign keyword) has to be wire, and any variable that is assigned using = inside an always or initial block has to be of type reg.


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