Cadence Tutorial 3: Generation of HSPICE
netlist from schematic using Analog Artist
Before starting this tutorial make sure you
have finished tutorial 1. Now that we have constructed the inverter from
tutorial 1, we are ready to generate the HSPICE netlist
and run the simulation
- From the
Composer-Schematic window select Tools ----> Analog Environment. The
Analog Environment Simulation window will appear as shown.
- Select Setup
---> Simulator/Directory/Host. The Choosing Simulator/directory/host
window will appear, from this window select the desired simulator to use
to perform your simulation. In this example, the chosen simulator is hspiceS. Click on OK.
- Select Simulation -> Netlist ->
Create Final to generate the netlist
- The netlist will be generated in a pop
up window. Click on File -> Save as to save the netlist
under a name.
Please refer to Chapter2 of Cadence Analog Design
Environment User Guide using cdsdoc
In case of any bug or comment
please email to pgolani@usc.edu or pabeerel@usc.edu