VLSI CAD Tools

Digital Circuit Simulation Using HSPICE - by C. Kime at U of Wisconsin
HSPICE Basics (from Stanford)
HSPICE Handout from Fall99 EE577A (ps and pdf) - by Sangyun Kim
Complete HSpice manual (.pdf).
On-line HSpice manual available via the command ~ee577/bin/get_hspice_help which if you have a web browser window open will take it over and re-direct you to the on-line hspice manual.

PowerView

PowerView Help Page (at UNCC)
Introduction to PowerView (ps and pdf) - by Prof. Puvvada
PowerView Tutorial - Inverter Schematic & Symbol - for the analog entry in PV by Jay Moon

Verilog-XL

Verilog for Behavioral Modeling (ps and pdf) - Lecture note of Verilog by Dr. Tzartzanis

Verilog Behavioral Modeling Ref Manual (ps and pdf) - sampled from Cadence online manual
Verilog-XL Tutorial (ps and pdf) - sampled from Cadence online manual
A neat verilog tutorial that runs on PC's is available for free from a company called Aldec. (See Aldec's home page for more details.)

PLA Tools

Cadence

Setup Tutorial (08/30/2004)
To view on-line Cadence help after setup, all you need to do is run cdsdoc on your Unix command line. This should open up a window that will allow you to peruse all available on-line documentation for Cadence. It is quite useful!
Cadence Tutorial0- Cadence Tutorial - 8-bit Adder Schematic & Symbol (01/20/2000)
Cadence Tutorial1 - Schematic Entry for Basic Gate (pdf) (01/20/2000)
Cadence Tutorial2 - Schematic Entry for 8-bit Adder (pdf) (01/20/2000)
Cadence Tutorial3 - Running Verilog-XL Simulation (pdf) (01/20/2000)
Cadence Tutorial4 - Simulating a Schematic with Verilog-XL (pdf) (01/20/2000)
Cadence Tutorial4 (extension) - Using simWaves in Integration Control (02/02/2000)
Cadence Tutorial5 - Comparing Verilog-XL Simulation (pdf) (01/20/2000)
Cadence Tutorial6 - Verilog-XL Simulation for Dymanic Logic (pdf) (01/20/2000)
Cadence Tutorial7 - Generating HSPICE Netlist from Schematic (pdf) (01/20/2000)
Cadence Tutorial8 - Symbol Editing and Verilog Association (01/20/2000)
Cadence Tutorial9 - Automatic Symbol Generation from Verilog and Schematic (01/20/2000)
Cadence Tutorial10 - Integrating the design with testbench (02/02/2000)
Magic Setup for TSMC 0.25 um (04/08/2000)