mipssim.h Source File

00001 // mipssim.h 
00002 //      Internal data structures for simulating the MIPS instruction set.
00003 //
00004 //  DO NOT CHANGE -- part of the machine emulation
00005 //
00006 // Copyright (c) 1992-1993 The Regents of the University of California.
00007 // All rights reserved.  See copyright.h for copyright notice and limitation 
00008 // of liability and disclaimer of warranty provisions.
00009 
00010 #ifndef MIPSSIM_H
00011 #define MIPSSIM_H
00012 
00013 #include "copyright.h"
00014 
00015 /*
00016  * OpCode values.  The names are straight from the MIPS
00017  * manual except for the following special ones:
00018  *
00019  * OP_UNIMP -           means that this instruction is legal, but hasn't
00020  *                      been implemented in the simulator yet.
00021  * OP_RES -             means that this is a reserved opcode (it isn't
00022  *                      supported by the architecture).
00023  */
00024 
00025 #define OP_ADD          1
00026 #define OP_ADDI         2
00027 #define OP_ADDIU        3
00028 #define OP_ADDU         4
00029 #define OP_AND          5
00030 #define OP_ANDI         6
00031 #define OP_BEQ          7
00032 #define OP_BGEZ         8
00033 #define OP_BGEZAL       9
00034 #define OP_BGTZ         10
00035 #define OP_BLEZ         11
00036 #define OP_BLTZ         12
00037 #define OP_BLTZAL       13
00038 #define OP_BNE          14
00039 
00040 #define OP_DIV          16
00041 #define OP_DIVU         17
00042 #define OP_J            18
00043 #define OP_JAL          19
00044 #define OP_JALR         20
00045 #define OP_JR           21
00046 #define OP_LB           22
00047 #define OP_LBU          23
00048 #define OP_LH           24
00049 #define OP_LHU          25
00050 #define OP_LUI          26
00051 #define OP_LW           27
00052 #define OP_LWL          28
00053 #define OP_LWR          29
00054 
00055 #define OP_MFHI         31
00056 #define OP_MFLO         32
00057 
00058 #define OP_MTHI         34
00059 #define OP_MTLO         35
00060 #define OP_MULT         36
00061 #define OP_MULTU        37
00062 #define OP_NOR          38
00063 #define OP_OR           39
00064 #define OP_ORI          40
00065 #define OP_RFE          41
00066 #define OP_SB           42
00067 #define OP_SH           43
00068 #define OP_SLL          44
00069 #define OP_SLLV         45
00070 #define OP_SLT          46
00071 #define OP_SLTI         47
00072 #define OP_SLTIU        48
00073 #define OP_SLTU         49
00074 #define OP_SRA          50
00075 #define OP_SRAV         51
00076 #define OP_SRL          52
00077 #define OP_SRLV         53
00078 #define OP_SUB          54
00079 #define OP_SUBU         55
00080 #define OP_SW           56
00081 #define OP_SWL          57
00082 #define OP_SWR          58
00083 #define OP_XOR          59
00084 #define OP_XORI         60
00085 #define OP_SYSCALL      61
00086 #define OP_UNIMP        62
00087 #define OP_RES          63
00088 #define MaxOpcode       63
00089 
00090 /*
00091  * Miscellaneous definitions:
00092  */
00093 
00094 #define IndexToAddr(x) ((x) << 2)
00095 
00096 #define SIGN_BIT        0x80000000
00097 #define R31             31
00098 
00099 /*
00100  * The table below is used to translate bits 31:26 of the instruction
00101  * into a value suitable for the "opCode" field of a MemWord structure,
00102  * or into a special value for further decoding.
00103  */
00104 
00105 #define SPECIAL 100
00106 #define BCOND   101
00107 
00108 #define IFMT 1
00109 #define JFMT 2
00110 #define RFMT 3
00111 
00112 struct OpInfo {
00113     int opCode;         /* Translated op code. */
00114     int format;         /* Format type (IFMT or JFMT or RFMT) */
00115 };
00116 
00117 static OpInfo opTable[] = {
00118     {SPECIAL, RFMT}, {BCOND, IFMT}, {OP_J, JFMT}, {OP_JAL, JFMT},
00119     {OP_BEQ, IFMT}, {OP_BNE, IFMT}, {OP_BLEZ, IFMT}, {OP_BGTZ, IFMT},
00120     {OP_ADDI, IFMT}, {OP_ADDIU, IFMT}, {OP_SLTI, IFMT}, {OP_SLTIU, IFMT},
00121     {OP_ANDI, IFMT}, {OP_ORI, IFMT}, {OP_XORI, IFMT}, {OP_LUI, IFMT},
00122     {OP_UNIMP, IFMT}, {OP_UNIMP, IFMT}, {OP_UNIMP, IFMT}, {OP_UNIMP, IFMT},
00123     {OP_RES, IFMT}, {OP_RES, IFMT}, {OP_RES, IFMT}, {OP_RES, IFMT},
00124     {OP_RES, IFMT}, {OP_RES, IFMT}, {OP_RES, IFMT}, {OP_RES, IFMT},
00125     {OP_RES, IFMT}, {OP_RES, IFMT}, {OP_RES, IFMT}, {OP_RES, IFMT},
00126     {OP_LB, IFMT}, {OP_LH, IFMT}, {OP_LWL, IFMT}, {OP_LW, IFMT},
00127     {OP_LBU, IFMT}, {OP_LHU, IFMT}, {OP_LWR, IFMT}, {OP_RES, IFMT},
00128     {OP_SB, IFMT}, {OP_SH, IFMT}, {OP_SWL, IFMT}, {OP_SW, IFMT},
00129     {OP_RES, IFMT}, {OP_RES, IFMT}, {OP_SWR, IFMT}, {OP_RES, IFMT},
00130     {OP_UNIMP, IFMT}, {OP_UNIMP, IFMT}, {OP_UNIMP, IFMT}, {OP_UNIMP, IFMT},
00131     {OP_RES, IFMT}, {OP_RES, IFMT}, {OP_RES, IFMT}, {OP_RES, IFMT},
00132     {OP_UNIMP, IFMT}, {OP_UNIMP, IFMT}, {OP_UNIMP, IFMT}, {OP_UNIMP, IFMT},
00133     {OP_RES, IFMT}, {OP_RES, IFMT}, {OP_RES, IFMT}, {OP_RES, IFMT}
00134 };
00135 
00136 /*
00137  * The table below is used to convert the "funct" field of SPECIAL
00138  * instructions into the "opCode" field of a MemWord.
00139  */
00140 
00141 static int specialTable[] = {
00142     OP_SLL, OP_RES, OP_SRL, OP_SRA, OP_SLLV, OP_RES, OP_SRLV, OP_SRAV,
00143     OP_JR, OP_JALR, OP_RES, OP_RES, OP_SYSCALL, OP_UNIMP, OP_RES, OP_RES,
00144     OP_MFHI, OP_MTHI, OP_MFLO, OP_MTLO, OP_RES, OP_RES, OP_RES, OP_RES,
00145     OP_MULT, OP_MULTU, OP_DIV, OP_DIVU, OP_RES, OP_RES, OP_RES, OP_RES,
00146     OP_ADD, OP_ADDU, OP_SUB, OP_SUBU, OP_AND, OP_OR, OP_XOR, OP_NOR,
00147     OP_RES, OP_RES, OP_SLT, OP_SLTU, OP_RES, OP_RES, OP_RES, OP_RES,
00148     OP_RES, OP_RES, OP_RES, OP_RES, OP_RES, OP_RES, OP_RES, OP_RES,
00149     OP_RES, OP_RES, OP_RES, OP_RES, OP_RES, OP_RES, OP_RES, OP_RES
00150 };
00151 
00152 
00153 // Stuff to help print out each instruction, for debugging
00154 
00155 enum RegType { NONE, RS, RT, RD, EXTRA }; 
00156 
00157 struct OpString {
00158     char *string;       // Printed version of instruction
00159     RegType args[3];
00160 };
00161 
00162 static struct OpString opStrings[] = {
00163         {"Shouldn't happen", {NONE, NONE, NONE}},
00164         {"ADD r%d,r%d,r%d", {RD, RS, RT}},
00165         {"ADDI r%d,r%d,%d", {RT, RS, EXTRA}},
00166         {"ADDIU r%d,r%d,%d", {RT, RS, EXTRA}},
00167         {"ADDU r%d,r%d,r%d", {RD, RS, RT}},
00168         {"AND r%d,r%d,r%d", {RD, RS, RT}},
00169         {"ANDI r%d,r%d,%d", {RT, RS, EXTRA}},
00170         {"BEQ r%d,r%d,%d", {RS, RT, EXTRA}},
00171         {"BGEZ r%d,%d", {RS, EXTRA, NONE}},
00172         {"BGEZAL r%d,%d", {RS, EXTRA, NONE}},
00173         {"BGTZ r%d,%d", {RS, EXTRA, NONE}},
00174         {"BLEZ r%d,%d", {RS, EXTRA, NONE}},
00175         {"BLTZ r%d,%d", {RS, EXTRA, NONE}},
00176         {"BLTZAL r%d,%d", {RS, EXTRA, NONE}},
00177         {"BNE r%d,r%d,%d", {RS, RT, EXTRA}},
00178         {"Shouldn't happen", {NONE, NONE, NONE}},
00179         {"DIV r%d,r%d", {RS, RT, NONE}},
00180         {"DIVU r%d,r%d", {RS, RT, NONE}},
00181         {"J %d", {EXTRA, NONE, NONE}},
00182         {"JAL %d", {EXTRA, NONE, NONE}},
00183         {"JALR r%d,r%d", {RD, RS, NONE}},
00184         {"JR r%d,r%d", {RD, RS, NONE}},
00185         {"LB r%d,%d(r%d)", {RT, EXTRA, RS}},
00186         {"LBU r%d,%d(r%d)", {RT, EXTRA, RS}},
00187         {"LH r%d,%d(r%d)", {RT, EXTRA, RS}},
00188         {"LHU r%d,%d(r%d)", {RT, EXTRA, RS}},
00189         {"LUI r%d,%d", {RT, EXTRA, NONE}},
00190         {"LW r%d,%d(r%d)", {RT, EXTRA, RS}},
00191         {"LWL r%d,%d(r%d)", {RT, EXTRA, RS}},
00192         {"LWR r%d,%d(r%d)", {RT, EXTRA, RS}},
00193         {"Shouldn't happen", {NONE, NONE, NONE}},
00194         {"MFHI r%d", {RD, NONE, NONE}},
00195         {"MFLO r%d", {RD, NONE, NONE}},
00196         {"Shouldn't happen", {NONE, NONE, NONE}},
00197         {"MTHI r%d", {RS, NONE, NONE}},
00198         {"MTLO r%d", {RS, NONE, NONE}},
00199         {"MULT r%d,r%d", {RS, RT, NONE}},
00200         {"MULTU r%d,r%d", {RS, RT, NONE}},
00201         {"NOR r%d,r%d,r%d", {RD, RS, RT}},
00202         {"OR r%d,r%d,r%d", {RD, RS, RT}},
00203         {"ORI r%d,r%d,%d", {RT, RS, EXTRA}},
00204         {"RFE", {NONE, NONE, NONE}},
00205         {"SB r%d,%d(r%d)", {RT, EXTRA, RS}},
00206         {"SH r%d,%d(r%d)", {RT, EXTRA, RS}},
00207         {"SLL r%d,r%d,%d", {RD, RT, EXTRA}},
00208         {"SLLV r%d,r%d,r%d", {RD, RT, RS}},
00209         {"SLT r%d,r%d,r%d", {RD, RS, RT}},
00210         {"SLTI r%d,r%d,%d", {RT, RS, EXTRA}},
00211         {"SLTIU r%d,r%d,%d", {RT, RS, EXTRA}},
00212         {"SLTU r%d,r%d,r%d", {RD, RS, RT}},
00213         {"SRA r%d,r%d,%d", {RD, RT, EXTRA}},
00214         {"SRAV r%d,r%d,r%d", {RD, RT, RS}},
00215         {"SRL r%d,r%d,%d", {RD, RT, EXTRA}},
00216         {"SRLV r%d,r%d,r%d", {RD, RT, RS}},
00217         {"SUB r%d,r%d,r%d", {RD, RS, RT}},
00218         {"SUBU r%d,r%d,r%d", {RD, RS, RT}},
00219         {"SW r%d,%d(r%d)", {RT, EXTRA, RS}},
00220         {"SWL r%d,%d(r%d)", {RT, EXTRA, RS}},
00221         {"SWR r%d,%d(r%d)", {RT, EXTRA, RS}},
00222         {"XOR r%d,r%d,r%d", {RD, RS, RT}},
00223         {"XORI r%d,r%d,%d", {RT, RS, EXTRA}},
00224         {"SYSCALL", {NONE, NONE, NONE}},
00225         {"Unimplemented", {NONE, NONE, NONE}},
00226         {"Reserved", {NONE, NONE, NONE}}
00227       };
00228 
00229 #endif // MIPSSIM_H