Academic Projects:  (Under Construction)

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-Resumé (15.OCT.2009)-

-Coursework (16.OCT.2009)-

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Digital Clock (EE-201L)

·         Time, alarm, timer and chronograph

·         Datapath, control unit and top level design implemented in Verilog HDL on FPGA

·         Design was tested and debugged for functionality with ModelSim

Prime Factorization (EE-201L)

·         Calculates the prime factorization of a number (0 to 255)

·         Datapath, control unit, and top level design implemented in Verilog HDL on FPGA

·         Design was tested and debugged for functionality with ModelSim

·         Design optimized for minimizing clock cycles used

Biomedical Computer Simulations (BME-210)

·         Simulations of the following implemented with MATLAB

o    Cardiac Output

o    Receptor-Ligand kinetics

o    Computerized tomography

o    Pharmacokinetics

o    Spread of disease

X-Ray Computed Tomography (BME-425)

·         Implemented the following algorithms on the Shepp-Logan phantom with MATLAB

o    Simple Back Projection

o    Filtered Back Projection

o    2D Direct Fourier Method (needs more work)

o    Iterative Methods

Electric Guitar (EE202L)

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[Page still under construction]