University of Southern California USC
Bardia Zandian - Home Page Viterbi
 
 

Research

 

Current Research:

My research has been on design and evaluation of novel solutions to mitigate circuit reliability issues. As devices scale to smaller dimensions, circuit lifetime reliability is reduced due to increased stress factors such as higher current density, electric field, and operation temperature. This problem is compounded as the number of these unreliable devices which are put on the same chip grows and process variations increase. Circuit reliability degradation stems from many electro-physical phenomena such as Electromigration, Time Dependant Dielectric Breakdown (TDDB), Hot Carrier Injection (HCI), and Negative Bias Temperature Instability (NBTI). These phenomena manifest as gradual timing degradation and eventual breakdown of circuits, this is referred to as wearout or aging which has been the main focus of my research. Design time prediction of expected wearout during the lifetime of a complex circuit, such as a high performance processor, is becoming increasingly challenging. This is due to dependence of the wearout causing phenomena on process variations, dynamically changing operation environment conditions, and workload-dependent circuit utilization. While these uncertainties existed even before, severity of their impact is increased as devices are scaled.

 

Past Research:

Research on 3D die stacking & its applications in Graphics Processing Unit design EE Department, USC, Los Angeles, CA

Research on selective destruction of individual carbon nanotubs by laser irradiation
EE Department, USC, Los Angeles, CA

Study of recognition algorithms and sensors for automated fingerprint recognition
ECE Department, Shahid Beheshti University, Tehran, Iran


01/2008-08/2008


02/2007-03/2008


02/2004-02/2005

 
Past Projects:
  • Designed and evaluated the performance of a runtime error detection subsystem       
  • Implemented a HIHO Viterbi Decoder using ncVerilog & synthesized the circuit
  • Designed and analyzed a high performance multistage op-amp
  • Designed and synthesized a WideWord (128 bit) 4-stage pipelined processor
  • Designed and simulated full schematic and layout of a Direct Digital Synthesizer
  • Created and tested an asynchronous 4x4 data crossbar using Verilog HDL
  • Implemented and tested a RTL neuron network circuit both in schematic and layout        
  • Design & development of a robot’s embedded control system with 8051 microcontroller   

Fall 2009
Spring 2008
Spring 2008
Spring 2008
Fall 2007
Fall 2007
Spring 2007
Spring 2002

 
 


 
             
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