My research has been on design and evaluation of novel solutions to mitigate circuit reliability issues. As devices scale to smaller dimensions, circuit lifetime reliability is reduced due to increased stress factors such as higher current density, electric field, and operation temperature. This problem is compounded as the number of these unreliable devices which are put on the same chip grows and process variations increase. Circuit reliability degradation stems from many electro-physical phenomena such as Electromigration, Time Dependant Dielectric Breakdown (TDDB), Hot Carrier Injection (HCI), and Negative Bias Temperature Instability (NBTI). These phenomena manifest as gradual timing degradation and eventual breakdown of circuits, this is referred to as wearout or aging which has been the main focus of my research. Design time prediction of expected wearout during the lifetime of a complex circuit, such as a high performance processor, is becoming increasingly challenging. This is due to dependence of the wearout causing phenomena on process variations, dynamically changing operation environment conditions, and workload-dependent circuit utilization. While these uncertainties existed even before, severity of their impact is increased as devices are scaled.
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