Rashed Zafar Bhatti's
Research and Projects Page

• Parcel Buffer (PBuf) for MONARCH (2005). Implemented PBuf a high bandwidth on-chip data/object router targeted to IBM Cu-8 processes. Synopsys Design Compiler and Prime Time is used for synthesis and timing analysis/closure.
    
• 2 Giga Bits SERDES design for IBM Cyclops Chip (2004). Design and implemented Serializer/De-serializer (SERDES) targeted to IBM-Cu-11 process. Random Sampling Technique is used to for duty cycle correction and data alignment.
    
• Automatic Test and Launch Control Systems (ATLCS) (2000 – 2001)
  Designed and Developed a Digital Automatic test and launch control system: Logic block engineered and tested in Verilog for Xilinx 4010 FPGA and Assembly level program for Control Logic based on 32 bit 8051 core Microcontroller. (Project Supervisor)
    
• Digital communication Unit for Loc Radar System (1997 – 1998)
  Designed and developed 8051 Microcontroller based remote data communication and interface units. Implemented Consumer and Producer control program to use a high-speed memory as FIFO.
  
• Communication Electronic Locating and Jamming Systems (1994 – 1996)
  Designed and developed the hardware interfaces boards for up gradation of the main computer to general purpose Pentium machine and control systems.

• Fused ALU and FPU. Verilog implementation and testing of a combined Integer and Floating Point Unit to exploited the reusability of the basic computing components to reduce the over all design area taken by two separate units.
   
• Viterbi Decoder Implementation. VHDL design of Viterbi Decoder with 12 deep path memory targeted to Xilinx Spartan-3 FPGA Platform, interfaced with PC parallel port through EPP core implemented in VHDL. Written a Visual Basic software to to send and receive the noisy and corrected data streams respectively for performance evaluation.
   
• Troy Router project. Designed Architecture of an on-chip packet switched network router. The design is implemented in Verilog HDL for latency and bandwidth performance analysis through simulations in ModelSim.
    
• High speed Low Power on chip Cache memory design. Proposed a new technique to associate the replacement policies with power minimization and management technique in the slumberous caches memories and SRAMS for future 90nm 70nm 65nm and 45nm fabrication processes.
     
• 0.18 micron SRAM Design. Complete design, floor planning, simulation and layout of 1024-kbit SRAM with 64-bit words using CADENCE VIRTUOSO, and HSPICE simulation. (High speed VLSI circuit design techniques are employed using DRCMOS and SRCMOS to achieve reduced access delay).
   
• PIM (Processor In Memory) 128 Bit Wide Word Processor. Design, implementation and simulation of 128 bit Wide Word Pipelined Processor core of PIM (Processors in Memory) in Verilog HDL using Verilog XL and NC Verilog of Cadence Tools set.
   
• 32 Bit Sliceable Adder, Shifter and Multiplier. Design and layout implementation of its 32 bit sliceable (byte, word, double word modes) ALU in MAGIC for 0.25micron process. The High speed multiplier optimized for 16 FO4 delay.
   
• FIFO Memory Design. Designed FIFO and its width and depth expansion controllers in VHDL using XILINX ISE Tools set and Synopsys FPGA Express. Implemented on XILINX SPARTAN FPGA.
   
• OCIN GEN. A software tool written in C++ that generates a Verilog HDL of On Chip Interconnection Network (OCIN) for a certain given network and routing parameters.
   
• Effects of Radiation and Hardening Techniques in deep sub-micron electronics. Studied and proposed radiation hardened cells designs, carried out MAGIC layouts and HSPICE simulations.
   
• Cardiac Signal Processor and Analyzer (Senior’s Project 1994). Designed a high speed digital circuit and PCB of a PC based data acquisition card to acquire signals from cardiac pick ups. Wrote software in TURBO PASCAL that controls the hardware and employs DSP algorithms of FFT for spectral analysis of cardiac signals and automatically detect the abnormality area of heart.
   
• SIMLAB (Junior Project 1993). A Hardware and Software project to digitize the input electronic signal for there spectral and behavioral analysis through complex mathematical and DSP algorithms. Received a Special Prize in All Pakistan Software Competition 1994.