- Fused ALU and FPU. Verilog implementation and testing
of a combined Integer and Floating Point Unit to exploited the reusability
of the basic computing components to reduce the over all design area
taken by two separate units.
- Viterbi Decoder Implementation. VHDL design of Viterbi
Decoder with 12 deep path memory targeted to Xilinx Spartan-3 FPGA Platform,
interfaced with PC parallel port through EPP core implemented in VHDL.
Written a Visual Basic software to to send and receive the noisy and
corrected data streams respectively for performance
- Troy Router project. Designed
Architecture of an on-chip packet switched network router. The design
is implemented in Verilog HDL for latency and bandwidth performance
analysis through simulations in ModelSim.
- High speed Low Power on chip Cache memory design.
Proposed a new technique to associate the replacement policies with
power minimization and management technique in the slumberous caches
memories and SRAMS for future 90nm 70nm 65nm and 45nm fabrication
- 0.18 micron SRAM Design. Complete design, floor
planning, simulation and layout of 1024-kbit SRAM with 64-bit words
using CADENCE VIRTUOSO, and HSPICE simulation. (High speed VLSI circuit
design techniques are employed using DRCMOS and SRCMOS to achieve
reduced access delay).
- PIM (Processor In Memory) 128 Bit Wide Word Processor.
Design, implementation and simulation of 128 bit Wide Word Pipelined
Processor core of PIM (Processors in Memory) in Verilog HDL using
Verilog XL and NC Verilog of Cadence Tools set.
- 32 Bit Sliceable Adder, Shifter and Multiplier. Design
and layout implementation of its 32 bit sliceable (byte, word, double
word modes) ALU in MAGIC for 0.25micron process. The High speed
multiplier optimized for 16 FO4 delay.
- FIFO Memory Design. Designed FIFO and its width and
depth expansion controllers in VHDL using XILINX ISE Tools set and
Synopsys FPGA Express. Implemented on XILINX SPARTAN FPGA.
- OCIN GEN. A software tool written in C++ that
generates a Verilog HDL of On Chip Interconnection Network (OCIN) for a
certain given network and routing parameters.
- Effects of Radiation and Hardening Techniques in deep
sub-micron electronics. Studied and proposed radiation hardened
cells designs, carried out MAGIC layouts and HSPICE simulations.
- Cardiac Signal Processor and Analyzer (Senior’s Project 1994).
Designed a high speed digital circuit and PCB of a PC based data
acquisition card to acquire signals from cardiac pick ups. Wrote
software in TURBO PASCAL that controls the hardware and employs DSP
algorithms of FFT for spectral analysis of cardiac signals and
automatically detect the abnormality area of heart.
- SIMLAB (Junior Project 1993). A Hardware and Software
project to digitize the input electronic signal for there spectral and
behavioral analysis through complex mathematical and DSP algorithms.
Received a Special Prize in All Pakistan Software Competition 1994.