Atit Jariwala is a graduate student at University of Southern California, Los Angeles specializing in Computer Architecture and VLSI. He recevied his B.S in Electronics Engineering from National Institute of Technology, Surat in 2012, where he was awarded Bronze Medal for his academic performance. He published two research papers in IEEE Journal implementing new architecture for Image processing algorithms on Virtex-5 FPGA. During his undergrad years, he also achieved first position in Freescale Cup 2011, India organized by Indian Institute of Science, Bangalore. His graduate studies at USC focuses on digital system design with the emphasis on timing and power optimization of CMOS Integrated Circuits. He is also tutoring EE457 students to help them understand the concepts of Computer Architecture.
 Das, S.; Jariwala, A.; Engineer, P., "Modified architecture for real-time face detection using FPGA," Engineering (NUiCONE), 2012 Nirma University International Conference on, vol., no., pp.1,5, 6-8 Dec. 2012
 Das, S.; Jariwala, A.; Engineer, P.; "FPGA based Stream processing for Edge and Skin detection algorithms", International Conference on Advanced Computing and Communication Technology, 3rd November 2012