Sireesh Adimadhyam
M.S in Electrical Engineering, 2012,
University of Southern California, Los Angeles
Hi!
My interest in
VLSI circuit design and device engineering has led me to take
the courses-
VLSI System Design,
Modern
Solid State Devices, VLSI
Computer Aided Design, Solid State Processing and
Integrated Circuits Laboratory, Computer System Organization
and Design
and MOS VLSI Circuit Design.
I have experience in CMOS circuit and layout design
using Cadence 6.0(TSMC20 and TSMC25 process) , Integrated
Circuit Fabrication and parametric testing and a background in Solid State
Devices. I have also worked on RTL Design using NC Verilog tool
and synthesis using DC_Shell.
I am currently looking for full time entry level and internship
positions in the field of
Electrical Engineering
with a focus in Digital System
Design and CMOS
Digital VLSI Design.
I enjoy working with different ECAD tools like Cadence-Virtuoso [CMOS
schematic and layout],
NCVerilog(system level abstraction), Eagle, OrCAD(component and board
level), Tina-Pro(circuit
simulation) and
most recently Fritzing(PCB design).
Contact:
You can e-mail me at:
adimadhy@usc.edu, sireeshadimadhyam@gmail.com
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