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Aayush Pathak

Graduate Student, VLSI Design
Ming Hsieh Department of Electrical Engineering
University of Southern California
aayushpa@usc.edu


About Me

Running water never grows stale, so you just have to 'Keep On Flowing'

With his mantra in head, I am all buzzed up and flowing! A marathoner at heart, an Engineer by degree,
a Designer by profession. I love what I do or I do what I love! And as we say at USC,my alma mater, just #FightOn!


Technical Skills

Languages and Flows

RTL (Verilog/SystemVerilog/VHDL) ,
Synthesis, DFT,
Low Power,
Static Timing Analysis,
Place & Route,
Digital Design,
RTL – GDS-II Methodology,
MATLAB,
TCL/Tk, Perl,
C/C++, Basics of Java and HTML

Tools and OS

Cadence Encounter Digital Design Suite (RTL Compiler, EDIS, ETS, Tempus, EPS),
Cadence Virtuoso,
Synopsys IC Compiler,
OrCAD,
Tanner,
PSpice,
ModelSim,
Asynchronous Design Tools (Proteus, Minimalist, ClockFree, Petrify),
MATLAB,
UNIX, Windows, SUN Solaris


Industrial Projects

Project Engineer - Fujitsu Electronics (WIPRO Technologies) -June 2010 - Oct 2011

• Netlist to GDS-II Implementation

1. Did block level physical design implementation for a 45nm design of 800k+ size. Major responsibilities Place and Route, Static Timing Ananlysis and ECOs.


2. Did block level DFT implementation for a 65nm design of 870k+ size. Major responsibilities were DFT insertion, pattern generation and pattern validation using Fujitsu's custom DFT flow. Did Stuck-at, Transient, MBIST and IDDQ DFT testing


3. Did block level Netlist to GDS-II implementation for a 45nm design of 700k+ size. Major responsibilities included Netlist Optimization, Place and Route, Clock Tree Synthesis, Static Timing Analysis, DRC-Clean Up, IR and EM Checks.



Member of Technical Staff - Cadence Design Systems, Inc - Oct 2011 - Aug 2014


1. Development and Verification of Physical Aware Mapping and Structuring with Probabilistic RC Extraction Methodologies in Cadence RTL Compiler


2. Validation of several Physical Aware Synthesis and Datapath Optimization methodologies for Cadence RTL Compiler

Worked with RnD team in validation of several Physical Aware RTL Synthesis features on customer multi-million cell count designs.
'Take a Bow’ Award was awarded for successful implementations and testing of the features developed.


3. Auto QoR Extraction Capability in RTL Compiler: Cadence In-House R&D Project.

Drafted the requirement Specification and developed the utilities to enable this capability in RTL Compiler which led to substantial improvement in QoR Reporting and Analysis.
‘Encore Award’ was awarded to the team for the successful development of this feature.


Academic Projects

University Of Southern California


1. • Design of 5-stage Pipelined CPU with Register Forwarding at the transistor level. (Virtuoso and Perl)


2. • Design, Validation and Gate Level Synthesis of Asynchronous NoC. (SystemVerilog, Modelsim, RTL Compiler, Proteus and ClockFree)


3. • Architect a Out-of-Order CPU with high MIPS under given area and transistor count limit. Enhanced my project by automating the validation of various architectures (SimpleScalar, HP Cacti)


4. • Design of ATPG System using PODEM and D-Algorithm. (C)


5. • Design of 1kB Cache Memory with LRU Replacement Policy for data Replacement. (Verilog, ModelSim)


6. • Circuit implementation and custom layout of Datapath components like multiplier, divider and Digital PLL (Virtuoso, Perl)


7. • Design of Virtual Reality based Google Maps 3D vision with Oculus VR - Winner “Virtual Awesomeness” Category at HACK-SC, Los Angeles’ premier hackathon at USC. (C# and MATLAB)


Indian Institute of Technology, Delhi


1. • Simulation of Kernighan and Lin Algorithm in MATLAB, with possible enhancements and used those in Ant-Colony Optimization based routing chip developed at IIT, Delhi (CAdence EDI, MATLAB) - Guide Dr. Jayadeva


Amity University, NOIDA, India


1. • Undergraduate Dissertation Project –Design & Development of PCO Module with Economic Calling Feature. Average statistical results showed 20% cost reduction with this switch adoption. (Embedded C)


2. • Undergraduate Minor Project – Development of Deployable Low-cost Outdoor Surveillance Vehicle System with Remote Access to Sensor Imagery


3. • Design & Development of Free Space Optics for Data Transmission & Hardware Implementation for Analog Data Transmission.



Awards and Accolades

University Of Southern California


2. Winner- Virtual Awesomeness Category - HackSc(LA's Premier hackathon at USC)
For design of Virtual Reality based Google Maps 3D vision with Oculus VR



Cadence Design Systems - Member of Technical Staff


1. ENCORE, R&D Award, Cadence Design Systems Inc. For the development of Automatic QoR extraction Mechanism.


2. Take a Bow, Product Engineering Award, Cadence Design Systems Inc. For the resolution of customer design issues and,
suggesting the design alterations without any change in functionality but with highly improved PPA results..


3. Well Done! Awards, Product Engineering Award, Cadence Design Systems Inc. 12 Well Done awrds for validating and,
developing various methodologies in RTL Compiler- Physical



Amity University, NOIDA, India


1. Bronze Medal for Academic Excellence - For Merit Rank 3, Amity University, Class of 2010


1. Citation, Best in Technical Innovation


1. Certificate of Merit - For Contribution made to VLSI Design Club, Amity School of Engineering and Technology


1. President's Scholarshipe - For complete full-time undergraduate studies at Amity University



Coursework @ USC

Semester - I


Digital VLSI Design [EE477L]
Computer Systems Organization [EE457]
Diagnosis and Design of Reliable Digital Computers [EE658]

Semester - II


Digital VLSI System Design [EE577A]
Computer Systems Architecture [EE557]
iAsynchronous VLSI Design [EE552]

My Resume

Here is my Resume. Thanks for considering!



Contact Me

For any internship/ Full Time opportunities please contact me at :
Phone : +1-213-477-3984 or write to me at :


aayushpa@usc.edu